Semiconductor device and method for fabricating the same

• US 7,612,375 B2
• Filed: 04/24/2003
• Issued: 11/03/2009
• Est. Priority Date: 04/24/2002
• Status: Expired due to Fees

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Makita, Naoki
• Primary Examiner(s): Nadav; Ori
• Application Number:
  US10/421,841
• Publication Number:
  US 20030201442A1
• Time in Patent Office: 2,385 Days
• Field of Search: 257 55- 61, 257 66- 72, 257347-354, 257/368, 257/369, 257/52, 257/75, 438/473, 438/166, 438/152
• US Class Current: 257/61
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1229 with different crystal properties within a device or between different devices
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1277 using a crystallisation promoting species, e.g. local introduction of Ni catalyst
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate

Abstract

A semiconductor device includes at least one thin-film transistor, which includes a semiconductor layer, a gate electrode and a gate insulating film. In the semiconductor layer, a crystalline region, including a channel forming region, a source region and a drain region, is defined. The gate electrode is provided to control the conductivity of the channel forming region. The gate insulating film is provided between the gate electrode and the semiconductor layer. The semiconductor layer includes a gettering region outside of the crystalline region thereof.

Claims

1. A semiconductor device comprising at least one thin-film transistor, the thin-film transistor including:

a semiconductor layer, including at least one catalytic element for promoting crystallization, in which a crystalline region, including a channel forming region, a source region and a drain region, is defined;

a gate electrode for controlling the conductivity of the channel forming region; and

a gate insulating film, which is provided between the gate electrode and the semiconductor layer, wherein,

when the thin-film transistor operates, the semiconductor layer includes a gettering region having an amorphous phase outside of the crystalline region thereof adjacent to the source region or the drain region,

the at least one catalytic element is included in each of the gettering region, the channel forming region, the source region and the drain region,

a concentration of the at least one catalytic element in the gettering region is higher than the concentration of the at least one catalytic element in each of the channel forming region, the source region and the drain region, individually, and

the at least one catalytic element is selected from the group consisting of Ni, Co, Sn, Pb, Pd, Fe and Cu.

2. The device of claim 1, wherein the gettering region is partially amorphous.

3. The device of claim 1, wherein the gettering region is substantially completely amorphous.

4. The device of claim 1, wherein the percentage of the gettering region that is amorphous is greater than the percentage of the channel forming region that is amorphous, the percentage of the source region that is amorphous and the percentage of the drain region that is amorphous.

5. The device of claim 1, wherein the semiconductor layer is made of Si, and

wherein the gettering region has a higher Pa/Pc ratio than the channel forming region, where the Pa/Pc ratio is a ratio of a TO phonon peak Pa of amorphous Si to a TO phonon peak Pc of crystalline Si in a Raman spectrum.

6. The device of claim 5, wherein the gettering region has a higher Pa/Pc ratio than the source region or the drain region.

7. The device of claim 1, wherein the gettering region is not adjacent to the channel forming region.

8. The device of claim 1, wherein the gettering region is located outside of a portion of the semiconductor layer, in which an interconnect, connecting respective thin-film transistors together electrically, contacts with the semiconductor layer.

9. The device of claim 1, wherein the gettering region is located at an outer edge of the semiconductor layer, and

wherein the contact portion between the interconnect and the semiconductor layer overlaps with a portion of the gettering region and a portion of the crystalline region.

10. The device of claim 1, wherein the gettering region is located at an outer edge of the semiconductor layer, and

wherein the contact portion between the interconnect and the semiconductor layer overlaps with the crystalline region only.

11. The device of claim 1, wherein multiple thin-film transistors are allocated to the single semiconductor layer and at least two of the thin-film transistors share the source region or the drain region, and

wherein the gettering region is located adjacent to the source region or the drain region that is shared by the at least two thin-film transistors.

12. The device of claim 1, wherein the gettering regions are provided at the outer edges of the semiconductor layer and between the source regions, between the drain regions or between the source and drain regions, and

wherein the contact portion between the interconnect and the semiconductor layer overlaps with a portion of one of the gettering regions and a portion of the crystalline region.

13. The device of claim 1, wherein the gettering regions are provided at the outer edges of the semiconductor layer and between the source regions, between the drain regions or between the source and drain regions, and

wherein the contact portion between the interconnect and the semiconductor layer overlaps with the crystalline region only.

22. The device of claim 1 or 14, wherein the gettering region includes an n-type dopant element belonging to Group Vb of the periodic table and a p-type dopant element belonging to Group IIIb of the periodic table.

23. The device of claim 22, wherein the gettering region includes the n-type dopant element at a concentration of about 1×

10¹⁹/cm³ to about 1×

10²¹/cm³ and the p-type dopant element at a concentration of about 1.5×

10¹⁹/cm³ to about 3×

10²¹/cm³.

24. The device of claim 22, wherein in the gettering region, the concentration of the p-type dopant element is about 1.5 to about 3.0 times as high as that of the n-type dopant element.

25. The device of claim 1 or 14, wherein the gettering region is doped with at least one rare-gas element that is selected from the group consisting of Ar, Kr and Xe.

26. The device of claim 25, wherein the gettering region is doped with the rare-gas element at a dose of about 1×

10¹⁹/cm³ to about 3×

10²¹/cm³.

27. The device of claim 1 or 14, wherein the gettering region includes the catalytic element at a dose of at least about 1×

10¹⁹/cm³.

28. The device of claim 1 or 14, wherein the gate electrode is made of at least one material that is selected from the group consisting of W, Ta, Ti and Mo.

29. An electronic appliance comprising the semiconductor device of claim 1.

30. The electronic appliance of claim 29, further comprising a display section that conducts a display operation by using the semiconductor device.

14. A semiconductor device comprising an n-channel thin-film transistor and a p-channel thin-film transistor,

wherein the n-channel thin-film transistor and the p-channel thin-film transistor each include:

a semiconductor layer, including at least one catalytic element for promoting crystallization, in which a crystalline region, including a channel forming region, a source region and a drain region, is defined;

a semiconductor layer, including at least one catalytic element for promoting crystallization, in which a crystalline region, including a channel forming region, a source region and a drain region, is defined;

a gate electrode for controlling the conductivity of the channel forming region; and

a gate insulating film, which is provided between the gate electrode and the semiconductor layer, wherein,

when the thin-film transistor operates, the semiconductor layer includes a gettering region having an amorphous phase outside of the crystalline region thereof adjacent to the source region or the drain region,

the at least one catalytic element is included in each of the gettering region, the channel forming region, the source region and the drain region,

a concentration of the at least one catalytic element in the gettering region is higher than the concentration of the at least one catalytic element in each of the channel forming region, the source region and the drain region, individually, and

the at least one catalytic element is selected from the group consisting of Ni, Go, Sn, Pb, Pd, Fe and Cu.

15. The device of claim 14, wherein the gettering region is partially amorphous.

16. The device of claim 14, wherein the gettering region is substantially completely amorphous.

17. The device of claim 14, wherein the percentage of the gettering region that is amorphous is greater than the percentage of the channel forming region that is amorphous, the percentage of the source region that is amorphous and the percentage of the drain region that is amorphous.

18. The device of claim 14, wherein the semiconductor layer is made of Si, and

wherein the gettering region has a higher Pa/Pc ratio than the channel forming region, where the Pa/Pc ratio is a ratio of a TO phonon peak Pa of amorphous Si to a TO phonon peak Pc of crystalline Si in a Raman spectrum.

19. The device of claim 18, wherein the gettering region has a higher Pa/Pc ratio than the source region or the drain region.

20. The device of claim 14, wherein the ratio S/W of the area S of the gettering region in the n-channel thin-film transistor to the width W of the channel forming region thereof is approximately equal to the ratio S/W of the area S of the gettering region in the p-channel thin-film transistor to the width W of the channel forming region thereof.

21. The device of claim 14, wherein a distance L from a junction between the channel forming region and the source region or the drain region to the gettering region in the n-channel thin-film transistor is approximately equal to a distance L from a junction between the channel forming region and the source region or the drain region to the gettering region in the p-channel thin-film transistor.