Transistor, memory cell array and method of manufacturing a transistor
First Claim
1. An integrated circuit including a transistor, the transistor comprising:
- first and second source/drain regions formed in a semiconductor material and extending at least to a first depth with respect to a top surface of the semiconductor material;
a channel region disposed between the first and second source/drain regions and comprising a fin-like portion including a ridge with a top side and two lateral sides in a cross-section perpendicular to a first direction defined by a line extending between the first and second source/drain regions; and
a gate electrode disposed in a gate groove defined in a top surface of the semiconductor material between the first and second source/drain regions;
wherein a top surface of the gate electrode is disposed between the top surface of the semiconductor material and the first depth; and
wherein the gate electrode surrounds the ridge at the top side and the two lateral sides.
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Accused Products
Abstract
A transistor includes a first and second source/drain regions, a channel connecting the first and second source/drain regions, and a gate electrode to control an electrical current flowing in the channel. The gate electrode is disposed in a gate groove, the gate groove being defined in a top surface of a semiconductor substrate. The first and second source/drain regions extend at least to a depth d1, the depth d1 being measured from the top surface of the substrate. A top surface of the gate electrode is disposed beneath the top surface of the semiconductor substrate. A top surface of the gate electrode is disposed at a depth d2 which is less than the depth d1, the depth d2 being measured from the substrate surface.
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Citations
12 Claims
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1. An integrated circuit including a transistor, the transistor comprising:
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first and second source/drain regions formed in a semiconductor material and extending at least to a first depth with respect to a top surface of the semiconductor material; a channel region disposed between the first and second source/drain regions and comprising a fin-like portion including a ridge with a top side and two lateral sides in a cross-section perpendicular to a first direction defined by a line extending between the first and second source/drain regions; and a gate electrode disposed in a gate groove defined in a top surface of the semiconductor material between the first and second source/drain regions; wherein a top surface of the gate electrode is disposed between the top surface of the semiconductor material and the first depth; and wherein the gate electrode surrounds the ridge at the top side and the two lateral sides. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An integrated circuit including a memory cell array comprising:
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a plurality of bit lines extending in a first direction; a plurality of memory cells, each of the memory cells comprising a storage element and an access transistor configured to electrically couple the storage element to one of the bit lines, wherein individual ones of the access transistors are formed in a semiconductor material and comprise; doped portions arranged adjacent a top surface of the semiconductor material and extending to a first depth, wherein the doped portions of each of the access transistors comprise a first source/drain region and a second source/drain region; a channel region formed between the first and second source/drain regions and comprising a fin-like portion including a ridge with a top side and two lateral sides in a cross-section perpendicular to a first direction defined by a line extending between the first and second source/drain regions; and a gate electrode surrounding the ridge at the top side and the two lateral sides; and a plurality of word lines configured to address the access transistors and extending in a second direction intersecting the first direction; wherein a top surface of each of the word lines is disposed at a depth between the top surface of the semiconductor material and the first depth. - View Dependent Claims (8, 9, 10, 11, 12)
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Specification