MOS transistor device

• US 7,612,408 B2
• Filed: 11/24/2004
• Issued: 11/03/2009
• Est. Priority Date: 11/28/2003
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Zundel, Markus, Kotz, Dietmar, Peri, Hermann, Zelsacher, Rudolf
• Primary Examiner(s): Smith; Bradley K
• Assistant Examiner(s): Movva; Amar
• Application Number:
  US10/996,849
• Publication Number:
  US 20050116267A1
• Time in Patent Office: 1,805 Days
• Field of Search: 257328-330, 257/333, 257/E29.26
• US Class Current: 257/333
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The invention relates to a MOS transistor device of the trench type, in which, in a semiconductor region of a first conductivity type, within a deep gate trench extending in the vertical direction of the semiconductor region, a vertical gate electrode and a gate oxide with a field plate step insulating the latter are formed and, in an adjoining mesa region outside and laterally with respect to the deep trench, at the upper section thereof, a source electrode region of the first conductivity type and a body region of a second conductivity type with one or a plurality of assigned body contact are formed, a drain electrode region of the first conductivity type lying opposite the deep trench in the vertical direction. The MOS transistor has a deep body reinforcement of the second conductivity type below the body region at the location of the body contact, said body reinforcement lying deeper than the field plate step.

Claims

1. A trench transistor device having an upper semiconductor region and a lower semiconductor region, comprising:

a substrate layer provided in the lower semiconductor region;

at least a first and a second gate trench, each extending in a vertical direction through the upper semiconductor region and the lower semiconductor region toward but not into the substrate layer, and having a length defined in a first lateral direction and a thickness defined in a second lateral direction of the semiconductor regions, the first lateral direction crossing the second lateral direction;

a gate electrode projecting in the vertical direction into the gate trench, insulated via an outer gate oxide, the gate electrode having a gate step beginning at a transition from the upper semiconductor region to the lower semiconductor region defining a field plate in the upper semiconductor region where the gate oxide in the second lateral direction is thinner than in the lower semiconductor region; and

a dense trench mesa region formed in the upper semiconductor region in parallel with and between the first and second gate trenches, said dense trench mesa region having a length extending in the first lateral direction and a width in the second lateral direction between the first and second gate trenches which is less than 2.5 times a maximum thickness of the gate oxide in the gate trenches, said dense trench mesa region comprising the following semiconductor regions;

a source electrode, a body region extending below the source electrode, and a body contact region extending above the body region but not to a depth of the gate step;

a body reinforcement positioned below the body region only at the location of the body contact region and extending in vertical direction through a portion of the upper region to a depth below the gate step but not extending to the substrate layer; and

said source electrode and said body contact region being alternately provided at the top most section of the mesa region in the first lateral direction and widths of said source electrode, said body region, said body contact region and said body reinforcement defined in the second lateral direction being equal to the width of the mesa region.

2. The device of claim 1, wherein the device is formed in a semiconductor region, a substrate region and an epitaxial region.

3. The device of claim 2, comprising a drain electrode opposite the gate trench, in the substrate region.

4. The device of claim 1, wherein the gate oxide is much thicker in the lower region relative to the upper region.

5. The device of claim 1, wherein the gate oxide is a silicon oxide.

6. The device of claim 1, wherein the gate electrode is thinner in the lower region relative to the upper region via the gate step.

7. The device of claim 1, wherein the source electrode is of a first conductivity type, and the body reinforcement is of a second conductivity type.

8. A MOS trench transistor device comprising:

a semiconductor region of a first conductivity type;

a vertical gate electrode;

a gate oxide insulating the vertical gate electrode, the vertical gate electrode formed within a deep vertical gate trench within the semiconductor region and having a length defined in a first lateral direction and a thickness defined in a second lateral direction of the semiconductor region, the first lateral direction crossing the second lateral direction;

a source electrode region of the first conductivity type at the upper section of a mesa region provided within the semiconductor region outside the gate trench and laterally and in parallel adjoining the gate trench, said mesa region having a length and a width, wherein the length of the mesa region extends in the first lateral direction and its width extends in the second lateral direction and said mesa region comprises;

below the source electrode region a semiconductor body region of a second conductivity type with one or a plurality of assigned semiconductor body contact regions, formed at the upper section of the mesa region;

the gate oxide being thinner in the upper section and undergoing a transition via a field plate step so as to be thicker in the lower section of the gate trench; and

a drain electrode region of the first conductivity type lying opposite the gate trench in the vertical direction; and

the MOS transistor device comprising a multiplicity of vertical MOS transistors, a gate trench and a mesa region alternating in the second lateral direction;

each mesa region being a dense trench mesa region which has with respect to an adjacent MOS transistor a width in the second lateral direction that is less than 2.5 times the maximum thickness of the gate oxide in the associated gate trench and in which plural source electrode regions and each body contact regions are successively and alternately provided in the length direction of the mesa region;

wherein the MOS transistor device furthermore has a deep body reinforcement of the second conductivity type which is provided below the semiconductor body region only at the locations of the body contact region and reaches into the depth of the semiconductor region below a field plate step of the gate oxide but not into a substrate region.

9. The MOS transistor device of claim 8, wherein the deep body reinforcement is formed by one or a plurality of staggered implantation.

10. The MOS transistor device of claim 8, wherein the deep body reinforcement is formed in a deep body reinforcement trench introduced into the semiconductor region.

11. The MOS transistor device of claim 8, wherein the deep body reinforcement is formed by a body reinforcement trench and by one or a plurality of adjoining implantations in the body reinforcement trench.

12. The MOS transistor device of claim 8, wherein the device forms a DMOS power transistor.

13. A MOS trench transistor device comprising:

a semiconductor region of a first conductivity type;

a vertical gate electrode;

a gate oxide insulating the vertical gate electrode formed within a deep vertical gate trench extending within the semiconductor region and having a length defined in a first lateral direction and a thickness defined in a second lateral direction of the semiconductor region, the first lateral direction crossing the second lateral direction;

a source electrode region of the first conductivity type in an upper section of a mesa region provided within the semiconductor region outside of the gate trench and laterally and in parallel adjoining the gate trench, said mesa region having a length and a width, wherein the length of the mesa region extends in the first lateral direction and its width extends in the second lateral direction and the mesa region comprises;

below the source region a semiconductor body region of a second conductivity type with one or a plurality of assigned semiconductor body contact region formed at the upper section of the mesa region;

the gate oxide being thinned in the upper section of the gate trench and undergoing transition via a field plate step to a second section situated in the lower section of the gate trench, and a drain electrode region of the first conductivity type lying opposite the gate trench in the vertical direction, and

the MOS transistor device comprising a multiplicity of vertical MOS transistors, a gate trench and a mesa region always being formed successively in a manner alternating in the second lateral direction, and

each mesa region being a dense trench mesa region which has with respect to an adjacent MOS transistor a width in the second lateral direction that is less than 2.5 times the maximum thickness of the gate oxide in the associated gate trench and in which plural source electrode regions and each semiconductor body contact regions are successively and alternately provided in the length direction of the mesa region; and

wherein the MOS transistor device furthermore has a deep body reinforcement of the second conductivity type which is provided below the semiconductor body region only at the locations of the body contact regions and reaches into the depth of the semiconductor region below a field plate step but not to a substrate region.

14. The MOS transistor device of claim 13, wherein the deep body reinforcement is formed in a deep body reinforcement trench introduced into the semiconductor region.

15. The MOS transistor device of claim 14, wherein the deep body reinforcement is formed by a body reinforcement trench and one or a plurality of adjoining implantations in the body reinforcement trench.

16. The MOS transistor device of claim 13, wherein the device forms a DMOS power transistor.