Dual-gate device and method

• US 7,612,411 B2
• Filed: 08/03/2005
• Issued: 11/03/2009
• Est. Priority Date: 08/03/2005
• Status: Active Grant

• Current Assignee: Schiltron Corporation (Infineon Technologies AG)
• Original Assignee: Schiltron Corporation (Infineon Technologies AG)
• Inventors: Walker, Andrew J.
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US11/197,462
• Publication Number:
  US 20070029618A1
• Time in Patent Office: 1,553 Days
• Field of Search: 257/368, 257/296, 257/314, 257/316, 257/347, 257/365, 257/392, 257/401
• US Class Current: 257/368
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor layer has a thickness, such that when a pass voltage is applied to the gate electrode of the access device, the access device and the memory device remains isolated, such that the charge stored in the memory device is unaffected by the pass voltage. The pass voltage is determined from a range of voltages, when applied to the access device, has no effect on the threshold voltage of the memory device. The dual-gate memory cells can be used as building blocks for a non-volatile memory array, such as a memory array formed by NAND-strings. In such an array, during programming of a nearby memory device in a NAND string, in NAND-strings not to be programmed, if inversion regions are allowed to be formed in the semiconductor layer, or if the semiconductor layer is allowed to electrically float, electrical interaction exists between the access devices and the memory devices to inhibit programming of the memory devices.

Claims

1. A dual-gate memory, comprising:

a dielectric layer having a planar surface;

a memory device and an access device located above the planar surface of the dielectric layer, wherein

the memory device has a channel region provided on a first surface of a semiconductor layer, a gate structure above the channel region, and a threshold voltage; and

the access device has a channel region provided on a second surface of the semiconductor layer, and a gate structure above the channel region, the second surface being provided on an opposite side of the semiconductor layer relative to the first surface, wherein the semiconductor layer is thick enough to substantially isolate the gate structure of the access device from the gate structure of the memory device, such that the threshold voltage of the memory device is substantially unchanged over a predetermined range of voltages applied on the gate structure of the access device that renders the access device conducting.

2. A dual-gate memory cell as in claim 1 wherein, when the second surface of the semiconductor layer is allowed to electrically float, electrical interaction exists between the access device and the memory device to inhibit programming of the memory device.

3. A dual-gate memory cell as in claim 1, wherein the semiconductor layer comprises polycrystalline semiconductor material.

4. A dual-gate memory cell as in claim 1, wherein the polycrystalline semiconductor material is selected from the group consisting of polycrystalline silicon, polycrystalline germanium, and a combination of polycrystalline silicon and polycrystalline germanium.

5. A dual-gate memory cell as in claim 1, wherein the memory device comprises a non-volatile memory device.

6. A dual-gate memory cell as in claim 5, wherein the memory device having a composite dielectric layer comprising silicon oxide and silicon nitride materials.

7. A dual-gate memory cell as in claim 6, wherein the silicon nitride material is selected from the group consisting of silicon nitride, silicon oxynitride, a silicon-rich silicon nitride and a silicon nitride having spatial variation of the silicon and oxygen contents.

8. A dual-gate memory cell as in claim 5, wherein the memory device comprises a floating conductor.

9. A dual-gate memory cell as in claim 8, wherein the floating conductor comprises nano-crystals placed between a gate electrode and the semiconductor layer.

10. A dual-gate memory cell as in claim 9, wherein the nano-crystals comprises a material selected from the group consisting of silicon, germanium, tungsten, and tungsten nitride.

11. A dual-gate memory cell as in claim 1, wherein the dual-gate memory cell is formed on an insulator.

12. A dual-gate memory cell as in claim 1, wherein the threshold voltage of the access device is substantially independent of the charge stored in the memory device over a predetermined range of charge.

13. A dual-gate memory cell as in claim 12, wherein the charge stored in the memory device is within the range of zero C/cm.sup.2 to 2 .mu.C/cm.sup.2.

14. A memory circuit comprising a NAND-type memory string, the NAND-type memory string comprising:

a bit line contact;

a source contact;

a plurality of dual-gate memory cells serially connected by source/drain regions, wherein (a) a first source/drain region at one end of the serially connected dual-gate memory cells is selectably, electrically coupled to the bit line contact and a second source/drain region at another end of the serially connected dual-gate memory cells is selectably, electrically coupled to source contact, and wherein (b) the dual-gate memory cells each comprise;

a dielectric layer having a planar surface;

a memory device and an access device located above the planar surface of the dielectric layer, wherein;

the memory device has a channel region provided on a first surface of a semiconductor layer, a gate structure above the channel region, and a threshold voltage; and

the access device has a channel region provided on a second surface of the semiconductor layer, and a gate structure above the channel region, the second surface being provided on an opposite side of the semiconductor layer relative to the first surface, wherein the semiconductor layer is thick enough to substantially isolate the gate structure of the access device from the gate structure of the memory device, such that the threshold voltage of the memory device is substantially unchanged over a predetermined range of voltages applied on the gate structure of the access device that renders the access device conducting.

15. A memory circuit as in claim 14 wherein the bit line contact and the first source/drain region are coupled through a select device;

16. A memory circuit as in claim 15, wherein the source contact and the second source/drain region are coupled through a select device.

17. A memory circuit as in claim 14 wherein, when the second surface of the semiconductor layer is allowed to electrically float, electrical interaction exists between the access device and the memory device to inhibit programming of the memory device.

18. A memory circuit as in claim 14, wherein, when programming one of the dual-gate memory cells, a first inversion channel region is formed in the channel region of the memory device of the dual-gate memory cells, and a second inversion channel is formed in an access device between the bit line contact and the dual-gate memory cell to be programmed, the first inversion channel being electrically connected to a predetermined voltage through the second inversion channel.

19. A memory circuit as in claim 14, wherein, when reading one of the dual-gate memory cells, an inversion channel region is formed in the channel region of an access device between the bit line contact and the dual-gate memory cell to be read, and wherein one of the source/drain regions adjacent the dual-gate memory cell to be read is electrically connected to a predetermined voltage through the inversion channel.

20. A memory circuit as in claim 14, further comprising a second NAND-type memory string substantially the same as the first NAND-type memory string, wherein corresponding gate electrodes of the memory devices in the first and second NAND-type memory strings are connected by a word line.

21. A memory circuit as in claim 20, wherein corresponding gate electrodes of the access devices in the first and second NAND-type memory strings are connected by a word line.

22. A memory circuit as in claim 20, wherein when programming a dual-gate memory cell in the first NAND-type memory string, a first predetermined voltage is applied to the bit line contact of the first NAND-type memory string, a voltage within the predetermined range of voltages is applied to the word lines connecting to access devices between the bit line contact and the dual-gate memory cell.

23. A memory circuit as in claim 22, wherein the word line connecting the corresponding gate electrodes of memory devices in the first and second NAND-type memory strings are applied a programming voltage, such that an inversion region is formed in the channel region of the memory device of the second NAND-type memory string, the inversion region being rendered electrically floating.

24. A memory circuit as in claim 22, wherein the source/drain regions in the second NAND-type memory string that are adjacent the dual-gate devices corresponding to dual gate memory cells between the bit line contact and the dual-gate memory cell in the first NAND-type memory string are allowed to electrically float.

25. A memory circuit as in claim 22, wherein when programming A dual-gate memory cell in the first NAND-type memory string, the bit line contact of the second NAND-type memory string is allowed to electrically float.

26. A memory circuit as in claim 22, wherein when programming a dual-gate memory cell in the first NAND-type memory string, the bit line contact of the second NAND-type memory string is connected to a predetermined voltage.

27. A memory circuit as in claim 22, wherein when programming a dual-gate memory cell in the first NAND-type memory string, the bit line contact of the first NAND-type memory string is applied a voltage within the predetermined range of voltages.

28. A memory circuit as in claim 14, wherein the dual-gate memory cells are fabricated on an insulator provided over a substrate.

29. A memory circuit as in claim 28, wherein the substrate comprises control circuits for controlling the NAND-type memory string.

30. A memory circuit as in claim 14, wherein the semiconductor layer comprises polycrystalline semiconductor material.

31. A memory circuit as in claim 30, wherein the polycrystalline semiconductor material is selected from the group consisting of polycrystalline silicon, polycrystalline germanium, and a combination of polycrystalline silicon and polycrystalline germanium.

32. A dual-gate memory cell, comprising:

a dielectric layer having a planar surface;

a memory device and an access device located above the planar surface of the dielectric layer, wherein

the memory device has a channel region provided on a first surface of a semiconductor layer, a gate structure above the channel region, and a threshold voltage; and

the access device has a channel region provided on a second surface of the semiconductor layer, and a gate structure above the channel region, the second surface being provided on an opposite side of the semiconductor layer relative to the first surface, wherein the semiconductor layer is thick enough to isolate a portion of the gate structure of the memory device from the gate structure of the access device, such that the threshold voltage of the memory device is substantially unchanged over a predetermined range of voltages applied on the gate structure of the access device that renders the access device conducting.

33. A memory circuit comprising a NAND-type memory string, the NAND-type memory string comprising:

a bit line contact;

a source contact;

a plurality of dual-gate memory cells serially connected by source/drain regions, wherein (a) a first source/drain region at one end of the serially connected dual-gate memory cells is selectably, electrically coupled to the bit line contact and a second source/drain region at another end of the serially connected dual-gate memory cells is selectably, electrically coupled to source contact, and wherein (b) the dual-gate memory cells each comprise;

a dielectric layer having a planar surface;

a memory device and an access device located above the planar surface of the dielectric layer, wherein

the memory device has a channel region provided on a first surface of a semiconductor layer, a gate structure above the channel region, and a threshold voltage; and

the access device has a channel region provided on a second surface of the semiconductor layer, and a gate structure above the channel region, the second surface being provided on an opposite side of the semiconductor layer relative to the first surface, wherein the semiconductor layer is thick enough to isolate a portion of the gate structure of the memory device from the gate structure of the access device, such that the threshold voltage of the memory device is substantially unchanged over a predetermined range of voltages applied on the gate structure of the access device that renders the access device conducting.