Inter-chip communication

• US 7,612,443 B1
• Filed: 09/03/2004
• Issued: 11/03/2009
• Est. Priority Date: 09/04/2003
• Status: Active Grant

• Current Assignee: University of Notre DAME Du Lac
• Original Assignee: University of Notre DAME Du Lac
• Inventors: Lui, Qing, Porod, Wolfgang, Bernstein, Gary H., Fay, Patrick
• Primary Examiner(s): Soward; Ida M
• Application Number:
  US10/933,417
• Time in Patent Office: 1,887 Days
• Field of Search: 257/685, 257/723, 257/773, 257/775, 257779-782, 257/786, 257/730, 257/E23.001, 257/E23.151, 257/E23.175
• US Class Current: 257/685
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/81141 Guiding structures both on and outside the body
• CPC Class Codes: H01L 2224/81224 using a laser
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/66 : of an individual connector
• CPC Class Codes: H01L 24/67 : of a plurality of connectors
• CPC Class Codes: H01L 24/72 : Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/167 : comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 29/0657 : characterised by the shape of the body
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10156 : at the periphery
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10271 : Silicon-germanium [SiGe]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H05K 1/181 : associated with surface mounted components
• CPC Class Codes: H05K 1/182 : associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
• CPC Class Codes: H05K 2201/0314 : Elastomeric connector or conductor, e.g. rubber with metallic filler
• CPC Class Codes: H05K 2201/10454 : Vertically mounted
• CPC Class Codes: H05K 2201/10909 : Materials of terminal, e.g. of leads or electrodes of components
• CPC Class Codes: H05K 3/326 : the printed circuit having integral resilient or deformable parts, e.g. tabs or parts of flexible circuits H05K3/365 takes precedence
• CPC Class Codes: H05K 3/328 : by welding
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product

Abstract

The present invention provides a quilt packaging system for microchip, a method for making such a quilt packaging system, microchips that may be used in a such a quilt packaging system, and methods for making such microchips.

Claims

1. A microchip comprising:

a plurality of first interconnect nodules, integrated with one or more edges of the microchip, each configured to make a direct electrical connection with one or more electrical contacts of one or more separate electronic devices, wherein said plurality of first interconnect nodules have at least two different shapes.

2. The microchip of claim 1, wherein said one or more edges comprise a plurality of edges.

3. The microchip of claim 1, wherein said one or more electronic devices comprise a plurality of electronic devices.

4. The microchip of claim 1, wherein said plurality of first interconnect nodules protrude from said one or more edges.

5. The microchip of claim 1, wherein said one or more electronic devices comprise a second microchip, and wherein said one or more electrical contacts comprise one or more second interconnect nodules.

6. The microchip of claim 1, wherein the microchip further comprises:

first alignment means configured to engage second alignment means of said electronic device to thereby align said one or more first interconnect nodules with said one or more electrical contacts of said electronic device.

7. The microchip of claim 6, wherein said electronic device is a second microchip, and wherein said one or more electrical contacts are one or more second interconnect nodules disposed on one or more edges of said second microchip.

8. The microchip of claim 7, wherein said first alignment means comprises a first modulated edge of the microchip and said second alignment means comprises a second modulated edge of said second microchip and wherein said one or more first interconnect nodules are disposed on said first modulated edge and wherein said one or more second interconnect nodules are disposed on said second modulated edge.

9. The microchip of claim 8, wherein said one or more first interconnect nodules comprise a plurality of first interconnect nodules and wherein said one or more second interconnect nodules comprise a plurality of second interconnect nodules.

10. The microchip of claim 6, wherein said first alignment means is integrated with the microchip.

11. The microchip of claim 6, wherein said first alignment means is shaped to restrictably engage said second alignment means along an axis of electrical communication of said one or more first interconnect nodules and said one or more electrical contacts.

12. The microchip of claim 11, wherein said one or more first interconnect nodules comprise a plurality of first interconnect nodules and wherein said one or more second interconnect nodules comprise a plurality of second interconnect nodules.

13. The microchip of claim 1, wherein said one or more first interconnect nodules are formed by depositing a conductive material on said one or more edges.

14. The microchip of claim 1, wherein said one or more first interconnect nodules have a male shape and said one or more electrical contacts have a female shape.

15. The microchip of claim 1, wherein said one or more first interconnect nodules have a female shape and said one or more electrical contacts have a male shape.

16. The microchip of claim 1, wherein said plurality of first interconnect nodules are disposed along two or more edges of the microchip, and wherein the interconnect nodules on a first edge of said two or more edges have a different shape than the interconnect nodules on a second edge of said two or more edges.

17. The microchip of claim 1, wherein said interconnect nodules on one edge of said one or more edges have at least two different shapes.

18. A microchip comprising:

one or more first interconnect nodules each configured to make a direct electrical connection with one or more electrical contacts of one or more separate electronic devices, wherein said one or more first interconnect nodules are integrated with one or more edges of the microchip,

wherein said one or more first interconnect nodules have a female shape and said one or more electrical contacts have a male shape.

19. The microchip of claim 18, wherein said one or more edges comprises a plurality of edges.

20. The microchip of claim 18, wherein said one or more electronic devices comprises a plurality of electronic devices.

21. The microchip of claim 18, wherein said one or more first interconnect nodules protrude from said one or more edges.

22. The microchip of claim 18, wherein said one or more electronic devices comprise a second microchip, and wherein said one or more electrical contacts comprise one or more second interconnect nodules.

23. The microchip of claim 18, wherein the microchip further comprises:

first alignment means configured to engage second alignment means of said electronic device to thereby align said one or more first interconnect nodules with said one or more electrical contacts of said electronic device.

24. The microchip of claim 23, wherein said electronic device is a second microchip, and wherein said one or more electrical contacts are one or more second interconnect nodules disposed on one or more edges of said second microchip.

25. The microchip of claim 24, wherein said first alignment means comprises a first modulated edge of the microchip and said second alignment means comprises a second modulated edge of said second microchip, and wherein said one or more first interconnect nodules are disposed on said first modulated edge and wherein said one or more second interconnect nodules are disposed on said second modulated edge.

26. The microchip of claim 25, wherein said one or more first interconnect nodules comprise a plurality of first interconnect nodules and wherein said one or more second interconnect nodules comprise a plurality of second interconnect nodules.

27. The microchip of claim 23, wherein said first alignment means is integrated with the microchip.

28. The microchip of claim 23, wherein said first alignment means is shaped to restrictably engage said second alignment means along an axis of electrical communication of said one or more first interconnect nodules and said one or more electrical contacts.

29. The microchip of claim 28, wherein said one or more first interconnect nodules comprise a plurality of first interconnect nodules and wherein said one or more second interconnect nodules comprise a plurality of second interconnect nodules.

30. The microchip of claim 18, wherein said one or more first interconnect nodules are formed by depositing a conductive material on said one or more edges.

31. The microchip of claim 18, wherein said one or more first interconnect nodules comprise a plurality of first interconnect nodules and wherein said one or more electrical contacts comprise a plurality of electrical contacts.

32. The microchip of claim 31, wherein said plurality of first interconnect nodules have at least two different shapes.

33. The microchip of claim 31, wherein said plurality of first interconnect nodules are disposed along two or more edges of of the microchip, and wherein the interconnect nodules on a first edge of said two or more edges have a different shape than the interconnect nodules on a second edge of said two or more edges.

34. The microchip of claim 31, wherein said interconnect nodules on one edge of said one or more edges have at least two different shapes.

35. A microchip comprising:

one or more interconnect nodules each configured to make a direct electrical connection with one or more electrical contacts a separate electronic device,

wherein said nodules are integrated with one or more edges of the microchip, and wherein at least one of said one or more interconnect nodules is deformable.

36. The microchip of claim 35, wherein at least one of said one or more interconnect modules protrude from at least one of said one or more edges.

37. The microchip of claim 35, wherein said electronic device has at least one edge having a male alignment element disposed thereon, the microchip further comprising:

a female alignment element disposed on at least one of said edges of the microchip configured to have said male alignment element inserted therein to align at least one interconnect module of the microchip with at least one electrical contact of said electronic device.

38. The microchip of claim 37, wherein said female alignment element comprises an alignment notch, and wherein said male alignment element comprises an alignment tab.

39. The microchip of claim 38, wherein said alignment notch has a concave trapezoidal shape, and wherein said alignment tab has a convex trapezoidal shape.

40. The microchip of claim 38, wherein said alignment notch has a concave rectangular shape, and wherein said alignment tab has a convex rectangular shape.

41. The microchip of claim 37, wherein at least one interconnect nodule of the microchip is disposed in said female alignment element, and wherein at least one electrical contact is disposed on said male alignment element.

42. The microchip of claim 35, wherein said electronic device has at least one edge having a female alignment element disposed thereon, the microchip further comprising:

a male alignment element disposed on at least one of said edges of the microchip configured to be inserted into said female alignment element to align at least one interconnect module of the microchip with at least one electrical contact of said electronic device.

43. The microchip of claim 42, wherein said female alignment element comprises an alignment notch, and wherein said male alignment element comprises an alignment tab.

44. The microchip of claim 43, wherein said alignment notch has a concave trapezoidal shape, and wherein said alignment tab has a convex trapezoidal shape.

45. The microchip of claim 43, wherein said alignment notch has a concave rectangular shape, and wherein said alignment tab has a convex rectangular shape.

46. The microchip of claim 42, wherein at least one interconnect nodule of the microchip is disposed on said male alignment element, and wherein at least one electrical contact is disposed in said female alignment element.