Switching frequency control of switched capacitor circuit using output voltage droop

• US 7,612,603 B1
• Filed: 06/05/2007
• Issued: 11/03/2009
• Est. Priority Date: 01/24/2007
• Status: Expired due to Fees

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Inventors: Petricek, Shea Lynn, Xing, Kun
• Primary Examiner(s): Donovan; Lincoln
• Assistant Examiner(s): O'Neill; Patrick
• Application Number:
  US11/758,513
• Time in Patent Office: 882 Days
• Field of Search: 327/306, 327/308, 327/309, 327/318, 327/323, 327/530, 327536-538, 327/543, 327/548, 363/62, 307/109, 307/110
• US Class Current: 327/530
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H02M 7/4837 Flying capacitor converters

Abstract

A frequency control circuit including a controlled oscillator and an amplifier circuit is disclosed for providing a clock signal to a switched capacitor circuit which divides an input voltage to provide an output voltage. The controlled oscillator has a frequency control input receiving a frequency control signal and an output for providing the clock signal at a frequency based on the frequency control signal. The amplifier circuit has an input for receiving the output voltage and an output providing the frequency control signal based on droop of the output voltage. In one embodiment, the amplifier circuit adjusts the frequency control signal to optimize efficiency of the switched capacitor circuit over a voltage range of the output voltage, which changes based on load level.

Claims

1. A capacitor voltage divider, comprising:

a switched capacitor circuit which provides an input voltage on an input node to provide an output voltage on an output node based on a clock signal; and

a frequency control circuit having an input receiving said output voltage and an output providing said clock signal, wherein said frequency control circuit continuously adjusts the frequency of said clock signal by an amount corresponding to the amount of droop of said output voltage.

2. The capacitor voltage divider of claim 1, wherein said frequency control circuit increases frequency of said clock signal with a decrease of said output voltage.

3. The capacitor voltage divider of claim 1, wherein said frequency control circuit comprises:

an amplifier circuit having an input receiving said output voltage and an output providing a frequency control signal; and

a controlled oscillator having an input receiving said frequency control signal and an output providing said clock signal.

4. The capacitor voltage divider of claim 3, wherein said amplifier circuit comprises a differential amplifier having a first input for sensing said output voltage, a second input receiving a reference voltage, and an output providing said frequency control signal.

5. The capacitor voltage divider of claim 4, further comprising a gain circuit having an input coupled to said input node and an output providing said reference voltage.

6. The capacitor voltage divider of claim 5, wherein said clock signal has a fixed duty cycle and wherein said gain circuit has a gain based on said duty cycle.

7. The capacitor voltage divider of claim 3, wherein said amplifier circuit comprises:

a differential amplifier having an inverting input, a non-inverting input receiving a reference voltage, and an output providing said frequency control signal as a voltage control signal;

a first resistor having one end coupled to said output node and a second end coupled to said inverting input of said differential amplifier; and

a second resistor having a first end coupled to said inverting input of said differential amplifier and a second end coupled to said output of said differential amplifier.

8. The capacitor voltage divider of claim 7, wherein said controlled oscillator comprises a voltage controlled oscillator.

9. The capacitor voltage divider of claim 3, wherein said controlled oscillator provides said clock signal with a fixed duty cycle, and provides said clock signal at a minimum frequency when said output voltage is at a nominal voltage level.

10. The capacitor voltage divider of claim 1, wherein said switched capacitor circuit comprises:

a first capacitor coupled between said input and output nodes;

a second capacitor coupled between said output node and a reference node;

a flying capacitor;

a first switching circuit which couples said flying capacitor in parallel with said first capacitor when said clock signal is at a first state; and

a second switching circuit which couples said flying capacitor in parallel with said second capacitor when said clock signal is at a second state.

11. The capacitor voltage divider of claim 10, wherein said switched capacitor circuit further comprises a switch driver having an input receiving said clock signal and a plurality of outputs controlling said first and second switching circuits.

12. A switched capacitor voltage converter, comprising:

a switched capacitor voltage divider which divides an input voltage to provide an output voltage based on an input clock signal, wherein said output voltage has a voltage droop based on output load current;

a controlled oscillator having a frequency control input receiving a frequency control signal and an output for providing said clock signal at a frequency based on said frequency control signal; and

an amplifier circuit having an input for receiving said output voltage and an output providing said frequency control signal which is continuously adjusted by an amount corresponding to the amount of said voltage droop of the output voltage.

13. The switched capacitor voltage converter of claim 12, wherein said amplifier circuit further comprises a gain circuit having an input for receiving said input voltage and an output providing a reference voltage, wherein said amplifier circuit determines said voltage droop based on a difference between said reference voltage and said output voltage.

14. The switched capacitor voltage converter of claim 12,

wherein said amplifier circuit further comprises:

said controlled oscillator having a fixed duty cycle; and

a gain circuit having an input for receiving said input voltage, an output providing a reference voltage and having a gain based on said fixed duty cycle of said controlled oscillator;

wherein said amplifier circuit determines said voltage droop based on a difference between said reference voltage and said output voltage.

15. The switched capacitor voltage converter of claim 12, wherein:

said controlled oscillator comprises a voltage controlled oscillator; and

wherein said amplifier circuit comprises;

a gain circuit having an input for receiving said input voltage and an output;

a first resistor having a first end receiving said output voltage and having a second end;

a second resistor having a first end coupled to said second end of said first resistor and having a second end; and

a differential amplifier having an inverting input coupled to said second end of said first resistor, a non-inverting input coupled to said output of said gain circuit, and an output coupled to said second end of said second resistor;

wherein said differential amplifier provides said frequency control signal as an adjustable voltage signal to adjust frequency of said clock signal.

16. A method of controlling a frequency of a switched capacitor circuit to optimize efficiency, comprising:

dividing an input voltage to provide an output voltage using a switched capacitor circuit which switches based on a clock signal;

providing the clock signal with a fixed duty cycle;

detecting an amount of droop of the output voltage; and

continuously adjusting the frequency of the clock signal by an amount corresponding to the detected amount of droop.

17. The method of claim 16, wherein said adjusting frequency comprises increasing the frequency of the clock signal in response to increasing output voltage droop.

18. The method of claim 16, wherein:

said detecting droop comprises;

multiplying the input voltage by a gain value to provide a reference voltage; and

amplifying a difference between the reference voltage and the output voltage to provide a frequency control signal; and

wherein said adjusting frequency comprises adjusting the frequency based on the frequency control signal.