Self-stabilizing differential load circuit with well controlled complex impedance

• US 7,612,609 B1
• Filed: 05/19/2008
• Issued: 11/03/2009
• Est. Priority Date: 05/19/2008
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Megaw, David James
• Primary Examiner(s): NGUYEN, PATRICIA T
• Application Number:
  US12/123,244
• Time in Patent Office: 533 Days
• Field of Search: 330/253, 330/302, 327/111
• US Class Current: 330/253
• CPC Class Codes: H03F 2203/45318 the AAC comprising a cross coupling circuit, e.g. two extra transistors cross coupled
• CPC Class Codes: H03F 2203/45631 the LC comprising one or more capacitors, e.g. coupling capacitors
• CPC Class Codes: H03F 2203/45696 the LC comprising more than two resistors
• CPC Class Codes: H03F 3/45273 Mirror types

Abstract

A circuit for providing a self-stabilizing, differential load circuit with well controlled complex impedance to an amplifier is described. According to an embodiment, two pairs of transistors in a cross-coupled configuration, a degeneration resistor for each transistor, and parasitic capacitance cancelation capacitors provide a self-stabilizing, differential load. Small signal analysis of the circuit illustrates an impedance of the load circuit to be substantially equal to a combination of impedance values with substantially little dependence on transconductances and incremental resistances of the transistors over an extended frequency range. By employing well matched resistors, impedance of the load to the amplifier can be controlled and common mode feedback loops avoided, because a current source is not employed as a load. The use of parasitic capacitance cancelation capacitors can substantially increase the bandwidth of the amplifier. Furthermore, with transistors, low voltage headroom may be increased and integrated circuit area decreased.

Claims

1. A differential load circuit for a differential amplifier, the differential load circuit comprising:

a first differential input having a first input capacitance;

a second differential input having a second input capacitance;

a first pair of transistors coupled to the first and the second differential inputs, the first pair of transistors being coupled to a first component having a complex impedance; and

a second pair of transistors coupled to the first and the second differential inputs, the second pair of transistors being coupled to a second component having a complex impedance, wherein, the complex impedances of the first and the second components are arranged to increase a bandwidth of the differential load circuit by cancelling the first and the second input capacitances.

2. The differential load circuit of claim 1, wherein the first and the second pairs of transistors are cross-coupled to each other.

3. The differential load circuit of claim 1, wherein the first and the second input capacitances are parasitic.

4. The differential load circuit of claim 1, wherein the first and the second component comprise a first resistor and a first capacitor, and a second resistor and a second capacitor, respectively.

5. The differential load circuit of claim 1, further comprising a first degeneration resistor coupled with the first pair of transistors and a second degeneration resistor coupled with the second pair of transistors.

6. The differential load of claim 1, wherein a load impedance of the differential load circuit is substantially dependent on the complex impedances of the first and the second components.

7. The differential load circuit of claim 1, wherein a load impedance of the differential load circuit is substantially independent of a transconductance of the first and the second pairs of transistors.

8. A differential load circuit for a differential amplifier, the differential load circuit comprising:

a first pair of matched transistors forming a first current source having a first input, the first input having a first input capacitance;

a second pair of matched transistors forming a second current source having a second input, the second input having a second input capacitance;

a first component having a first complex impedance coupled to the first pair of matched transistors; and

a second component having a second complex impedance coupled to the second pair of matched transistors, wherein the first and the second complex impedances are arranged to cancel the first and the second input capacitances to increase a bandwidth of the differential load circuit.

9. The differential load circuit of claim 8, wherein the first and the second pair of matched transistors are cross-coupled to each other.

10. The differential load circuit of claim 8, wherein the first and the second input capacitances are substantially equal.

11. The differential load circuit of claim 8, wherein the first and the second complex impedances are substantially equal.

12. The differential load circuit of claim 8, wherein the differential load circuit is self-stabilizing.

13. The differential load circuit of claim 8, wherein a load impedance of the differential load circuit is substantially dependent on the first and the second complex impedances.

14. The differential load circuit of claim 8, wherein a load impedance of the differential load is substantially independent of a transconductance of the first and the second pairs of matched transistors.

15. A method of increasing a bandwidth of a differential load circuit of a differential amplifier, the method comprising:

coupling an active load circuit to a first output and a second output of the differential amplifier, the active load comprising;

a first differential input having a first input capacitance;

a second differential input having a second input capacitance;

a first pair of transistors coupled to the first and the second differential inputs, the first pair of transistors being coupled to a first component having a complex impedance; and

a second pair of transistors coupled to the first and the second differential inputs, the second pair of transistors being coupled to a second component having a complex impedance; and

using the complex impedances of the first and the second components to cancel the first and the second input capacitances to increase the bandwidth of the differential load circuit.

16. The method of claim 15, further comprising using a first degeneration resistor coupled with the first pair of transistors and a second degeneration resistor coupled with the second pair of transistors to create an impedance of the differential load circuit.

17. The method of claim 15, wherein an impedance of the differential load circuit is substantially independent of a transconductance of the first and the second pairs of transistors.

18. The method of claim 15, wherein a load impedance of the differential load circuit is substantially dependent on the complex impedances of the first and the second components.

19. The method of claim 15, wherein the complex impedances of the first and the second components each comprise a resistance and at least one of a capacitance and an inductance.

20. The method of claim 19, wherein the using the complex impedances of the first and the second components comprises matching the capacitance of the complex impedances of the first and the second components with the first and the second input capacitances, respectively.