Sharing operational amplifier between two stages of pipelined ADC and/or two channels of signal processing circuitry

• US 7,612,701 B2
• Filed: 11/26/2008
• Issued: 11/03/2009
• Est. Priority Date: 08/26/2005
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Inventors: Cho, Taehee, Barna, Sandor L., Lever, Andrew M., Cho, Kwang-Bo, Lee, Chiajen
• Primary Examiner(s): WILLIAMS, HOWARD L
• Application Number:
  US12/323,640
• Publication Number:
  US 20090072899A1
• Time in Patent Office: 342 Days
• Field of Search: 341/161, 341/162, 341/163, 348/308
• US Class Current: 341/161
• CPC Class Codes: H03M 1/0607 Offset or drift compensation removal of offset already present on the analogue input signal H03M1/1295
• CPC Class Codes: H03M 1/0695 using less than the maximum number of output states per stage or step, e.g. 1.5 per stage or less than 1.5 bit per stage type
• CPC Class Codes: H03M 1/1225 using time-division multiplexing
• CPC Class Codes: H03M 1/442 using switched capacitors

Abstract

A mechanism for discharging parasitic capacitance at an input of an operational amplifier, which is shared between two stages of a pipelined analog-to-digital converter and/or two channels of signal processing circuitry, before the amplifier configuration of the stages/channels is switched. The discharging act occurs when a short reset pulse is generated between two clock phases. The short reset pulse is applied to a switch connected to the operational amplifier input. When the reset pulse closes the switch, a discharge path is created and any parasitic capacitance at the operational amplifier input is discharged through the path. The discharging of the parasitic capacitance substantially mitigates the memory effect and the problems associated with the memory effect.

Claims

1. An imager comprising:

a pixel array;

sample and hold circuitry coupled to receive analog signals from pixels within the array;

an amplification circuit for amplifying the analog signals; and

a pipelined analog-to-digital converter connected to receive and convert the amplified analog signals to digital signals, said converter comprising;

an amplifier,

first and second pipeline stages adapted to be switchably connected to the amplifier in response to first and second clock signals,

a discharge circuit adapted to cause a discharge operation to occur at an input of the amplifier in response to a reset pulse; and

a clock generator, said clock generator generating first and second clock signals and a plurality of reset pulses, the first and second clock signals being generated such that they are non-overlapping, said clock generator applying the first and second clock signals and the reset pulses to the pipeline stages and the discharge circuit to change the connections between the pipeline stages, discharge circuit and the amplifier.

2. The imager of claim 1, wherein the discharge operation occurs during a first period after the first clock signal, but before the second clock signal, in which the connections between the first and second pipeline stages and the amplifier switch and another discharge operation occurs at the input of the amplifier in response to another reset pulse during a second period after the second clock signal, but before the first clock signal, in which the connections between the first and second pipeline stages and the amplifier switch.

3. The imager of claim 1, wherein the discharge circuit is adapted to form a parasitic capacitance discharge path from the input of the amplifier to a discharge area during the discharge operation.

4. The imager of claim 1, wherein the discharge circuit comprises a switch coupled between a ground potential and the input the amplifier, wherein the switch is adapted to receive the reset pulse and connect the input of the amplifier to the ground potential in response to the reset pulse.

5. The imager of claim 1, wherein said first clock signal causes said first stage to have a first connection to the amplifier and to perform a first operation and said second stage to have a second connection to the amplifier and to perform a second operation.

6. The imager of claim 5, wherein said second clock signal causes said first stage to have the second connection to the amplifier and to perform the second operation and said second stage to have the first connection to the amplifier and to perform the first operation.

7. The imager of claim 1, wherein the reset pulses are generated after the first clock signal transitions from a first state to a second state and after the second clock signal transitions from the first state to the second state.

8. An imager comprising:

a pixel array; and

a readout circuit comprising;

first and second circuits coupled to receive analog signals from pixels within the array,

an amplifier adapted to be switchably connected between the first and second circuits, and

a discharge circuit adapted to be switchably connected to an input of the amplifier, the discharge circuit causing a discharge operation to occur at an input of the amplifier during a period in which the connections between the first and second circuits and the amplifier switch.

9. The imager of claim 8, wherein the discharge circuit comprises a switch coupled between a ground potential and the input of the amplifier, wherein the switch is adapted to receive a reset pulse and connect the input of the amplifier to the ground potential in response to the reset pulse.

10. The imager of claim 8, wherein the discharge operation forms a parasitic capacitance discharge path from the input of the amplifier to a discharge area.

11. The imager of claim 8, further comprises a clock generator adapted to generate non-overlapping first and second clock signals and a plurality of reset pulses, said clock generator adapted to apply the first and second clock signals and the reset pulses to the first and second circuits and the discharge circuit to change the connections between the circuits, discharge circuit and the amplifier.

12. The imager of claim 11, wherein the first clock signal causes said first circuit to have a first connection to the amplifier and to perform a first operation and said second circuit to have a second connection to the amplifier and to perform a second operation.

13. The imager of claim 12, wherein the second clock signal causes said first circuit to have the second connection to the amplifier and to perform the second operation and said second circuit to have the first connection to the amplifier and to perform the first operation.

14. The imager of claim 11, wherein the reset pulses cause the discharge circuit to have a connection between a discharge path and the input of the amplifier and to perform the discharge operation.

15. The imager of claim 11, wherein the reset pulses are generated after the first clock signal transitions from a first state to a second state and after the second clock signal transitions from the first state to the second state.

16. The imager of claim 8, wherein the first and second circuits are signal processing channels.

17. The imager of claim 8, wherein the first and second circuits are pipeline stages of an analog-to-digital converter.

18. A method of operating signal processing circuitry comprising two channels sharing an amplifier, said method comprises performing a first discharge operation at the amplifier during a first period in which portions of the first and second channels change operations.

19. The method of claim 18, wherein the first discharge operation is performed in response to a first reset pulse.

20. The method of claim 18, further comprising performing a second discharge operation at the amplifier during a second period in which the portions of the first and second channels change operations.