CMOS image sensor with noise cancellation

• US 7,612,817 B2
• Filed: 06/14/2004
• Issued: 11/03/2009
• Est. Priority Date: 11/06/2001
• Status: Expired due to Fees

• Current Assignee: Candela Microsystems Incorporated
• Original Assignee: Candela Microsystems Incorporated
• Inventors: Tay, Hiok Nam
• Primary Examiner(s): Tran; Sinh
• Assistant Examiner(s): Daniels; Anthony J
• Application Number:
  US10/868,407
• Publication Number:
  US 20040233312A1
• Time in Patent Office: 1,968 Days
• Field of Search: 348294-310, 250/208.1
• US Class Current: 348/308
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H04N 1/32358 using picture signal storage, e.g. at transmitter H04N1/17 takes precedence
• CPC Class Codes: H04N 1/32475 Changing the format of the data, e.g. parallel to serial or vice versa
• CPC Class Codes: H04N 1/32491 alternate storage in and retrieval from two parallel memories, e.g. using ping-pong buffers
• CPC Class Codes: H04N 1/40 Picture signal circuits H04N1/387 takes precedence
• CPC Class Codes: H04N 2201/0081 Image reader H04N2201/0091 - H04N2201/0094 take precedence
• CPC Class Codes: H04N 2201/3292 of one or two complete lines
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/70 SSIS architectures; Circuits associated therewith
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 25/771 comprising storage means other than floating diffusion
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
• CPC Class Codes: H04N 9/64 Circuits for processing colour signals H04N9/77 takes precedence; camera processing pipelines for processing colour signals H04N23/84
• CPC Class Codes: H04N 9/642 Multi-standard receivers

Abstract

An image sensor that has one or more pixels within a pixel array. The pixel array may be coupled to a control circuit and one or more subtraction circuits. The control circuit may cause each pixel to provide a first reference output signal and a reset output signal. The control circuit may then cause each pixel to provide a light response output signal and a second reference output signal. The light response output signal corresponds to the image that is to be captured by the sensor. The subtraction circuit may provide a difference between the reset output signal and the first reference output signal to create a noise signal that is stored in memory. The subtraction circuit may also provide a difference between the second reference output signal and the light response output signal to create a normalized light response output signal. The noise signal may then be subtracted from the normalized light response output signal to generate the output data of the sensor. The second reference output signal is the same as the first reference output signal so that the process in essence subtracts the reset noise from the light response signal.

Claims

1. An image sensor, comprising:

a photodetector;

an output transistor having a gate coupled to receive a signal from said photodetector;

a reset transistor having a drain terminal coupled to reset said photodetector;

a sample circuit coupled to receive an output signal from said output transistor; and

a control circuit having a configuration to switch said reset transistor to a triode region such that said output transistor provides a sampled first reference output signal and to subsequently switch said reset transistor to an OFF state such that said output transistor provides a sampled reset output signal that has a voltage different from a voltage of said sampled first reference output signal and a configuration to switch said sample circuit to sample and store said sampled first reference output signal when said reset transistor is in said triode region and to sample and store said sampled reset output signal when said reset transistor is in said OFF state.

2. The image sensor of claim 1, wherein said control circuit has a configuration to switch said output transistor to provide a sampled light response output signal, and to subsequently switch said reset transistor into a triode region such that said output transistor provides a sampled second reference output signal.

3. The image sensor of claim 2, further comprising a capacitor coupled to said output transistor to store said sampled first reference output signal and said sampled second reference output signal.

4. The image sensor of claim 1, wherein said control circuit has a configuration to switch a gate of said reset transistor into a tri-state that lasts at least up to a sampling of said sampled first reference output signal.

5. The image sensor of claim 2, wherein said voltage of said sampled first reference output signal is same as a voltage of said sampled second reference output signal.

6. An image sensor, comprising:

a photodetector;

a reset transistor having a drain terminal coupled to reset said photodetector;

an output transistor having a gate coupled to receive a signal from said photodetector;

a sample circuit coupled to receive an output signal from said output transistor; and

control means for switching said reset transistor into triode region so that said output transistor provides a sampled first reference output signal, for switching said reset transistor into an OFF state so that said output transistor provides a sampled reset output signal that has a voltage different from a voltage of said sampled first reference output signal and for directing said sample circuit to sample and store said sampled first reference output signal when said reset transistor is in said triode region and to sample and store said sampled reset output signal when said reset transistor is in said OFF state.

7. The image sensor of claim 6, wherein said control means is also for switching said output transistor to provide a sampled light response output signal and subsequently switching said reset transistor into a triode region such that said output transistor provides a sampled second reference output signal.

8. The image sensor of claim 6, further comprising a capacitor coupled to said output transistor to store said sampled first reference output signal and said sampled second reference output signal.

9. The image sensor of claim 6, wherein said control means is also for switching a gate of said reset transistor into a tri-state that lasts at least up to a sampling of said sampled first reference output signal.

10. The image sensor of claim 7, wherein said voltage of said sampled first reference output signal is same as a voltage of said sampled second reference output signal.

11. A method for generating signals from a pixel of an image sensor, the pixel having a reset transistor and an output transistor having a gate coupled to receive a signal from a photodetector, the reset transistor having a source terminal connected to receive a signal from an IN line and a drain terminal coupled to reset the photodetector, the output transistor being coupled to provide a signal to an OUT line, comprising:

switching the reset transistor into a triode region, providing a reference signal on the IN line so that an output reference signal is provided on the OUT line;

sampling said output reference signal while the reset transistor is in the triode region;

switching the reset transistor to an OFF state;

sampling a reset output signal provided on the OUT line while the reset transistor is in the OFF state, the reset output signal having a voltage different from a voltage of the output reference signal.

12. The method of claim 11, wherein a gate of the reset transistor is in a tri-state upon the sampling of the output reference signal.

13. The method of claim 12, further comprising:

providing a predetermined voltage on the IN line prior to the tri-state, the reset transistor in the triode region and having a lesser source-bulk reverse bias than when the reference signal is provided on the IN line.

14. The method of claim 13, wherein a gate voltage of the reset transistor has a change along with and in a same direction as a change of a source voltage of the reset transistor during the tri-state due to a capacitive coupling.

15. The method of claim 14, wherein said capacitive coupling is from a channel of the reset transistor to the gate of the reset transistor.

16. The method of claim 14, wherein said capacitive coupling is from a drain of the reset transistor to the gate of the reset transistor.

17. The method of claim 14, wherein said capacitive coupling is from a source of the reset transistor to the gate of the reset transistor.

18. An image sensor, comprising:

a photodetector;

a reset transistor having a drain terminal coupled to reset said photodetector;

an output transistor having a gate coupled to receive a signal from said drain terminal of said reset transistor, said output transistor configured to output a sampled first reference output signal when said reset transistor is in a triode region and a sampled reset output signal when said reset transistor is in an OFF state; and

a sample circuit configured to sample and store said sampled first reference output signal when said reset transistor is in said triode region and to sample and store said sampled reset output signal when said reset transistor is in said OFF state.

19. The image sensor of claim 18, wherein said output transistor is configured to provide a sampled light response output signal while said reset transistor is in an OFF state, and said reset transistor is configured to subsequently switch to a triode region to generate a sampled second reference output signal.

20. The image sensor of claim 18, wherein a gate of said reset transistor is configured to be in a tri-state when said sample circuit samples said sampled first reference output signal.

21. The image sensor of claim 20, wherein said drain terminal is configured to be at a predetermined voltage level prior to said tri-state such that said drain terminal has a drain-bulk reverse bias that is lesser than when said output transistor outputs said sampled first reference output signal.

22. The image sensor of claim 21, wherein a gate voltage of said reset transistor is configured to change along with a drain voltage of said reset transistor in a same direction during said tri-state through a capacitive coupling.

23. The image sensor of claim 22, wherein said reset transistor is configured to remain in said triode region during said change in said drain voltage level.

24. An image sensor, comprising:

a photodetector;

a reset transistor having a drain terminal coupled to reset said photodetector;

an output transistor having a gate coupled to receive a signal from said drain terminal of said reset transistor, said output transistor outputting a sampled first reference output signal when said reset transistor is in a triode region and a sampled reset output signal when said reset transistor is in an OFF state; and

a sample circuit that samples and stores said sampled first reference output signal when said reset transistor is in said triode region and that samples and stores said sampled reset output signal when said reset transistor is in said OFF state.

25. The image sensor of claim 24, wherein said output transistor provides a sampled light response output signal while said reset transistor is in an OFF state, and said reset transistor subsequently switches to a triode region to generate a sampled second reference output signal.

26. The image sensor of claim 24, wherein a gate of said reset transistor is in a tri-state when said sample circuit samples said sampled first reference output signal.

27. The image sensor of claim 26, wherein said drain terminal is at a predetermined voltage level prior to said tri-state such that said drain terminal has a drain-bulk reverse bias that is lesser than when said output transistor outputs said sampled first reference output signal.

28. The image sensor of claim 27, wherein a gate voltage of said reset transistor has a change along with and in a same direction as a change in a drain voltage of said reset transistor during said tri-state due to a capacitive coupling.

29. The image sensor of claim 28, wherein said reset transistor remains in said triode region during said change of said drain voltage.