Methods for operating semiconductor device and semiconductor memory device

• US 7,613,041 B2
• Filed: 09/25/2006
• Issued: 11/03/2009
• Est. Priority Date: 06/06/2003
• Status: Expired due to Fees

• Current Assignee: Marvell International Limited (Marvell Technology Group Limited), Marvell Semiconductor, Inc. (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Wang, Chih-Hsin
• Primary Examiner(s): Ho; Hoai V.
• Assistant Examiner(s): Lappas; Jason
• Application Number:
  US11/464,404
• Publication Number:
  US 20070008778A1
• Time in Patent Office: 1,135 Days
• Field of Search: 365/185.19, 365/174, 365/185.01
• US Class Current: 365/185.01
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

Abstract

Methods and apparatus on charges injection using piezo-ballistic-charges injection mechanism are provided for semiconductor device and nonvolatile memory device. The device comprises a strain source, an injection filter, a first conductive region, a second conductive region, and a third conductive region. The strain source permits piezo-effect in ballistic charges transport to enable the piezo-ballistic-charges injection mechanism in device operations. The injection filter permits transporting of charge carriers of one polarity type from the first conductive region, through the filter, and through the second conductive region to the third conductive region while blocking the transport of charge carriers of an opposite polarity from the second conductive region to the first conductive region. The present invention further provides an energy band engineering method permitting the devices be operated without suffering from disturbs, from dielectric breakdown, from impact ionization, and from undesirable RC effects.

Claims

1. A method of operating a semiconductor device having a strained tunneling gate, strained ballistic gate disposed adjacent to and insulated from the strained tunneling gate, a storage region disposed adjacent to and insulated from the strained ballistic gate, and a strain source providing a mechanical stress to the strained tunneling gate and the strained ballistic gate to provide a piezo-effect, the method comprising the steps of:

applying a first voltage to the strained tunneling gate;

applying a second voltage to the strained ballistic gate; and

applying a third voltage to the storage region to inject charge carriers from the strained tunneling gate through the strained ballistic gate into the storage region.

2. The method of claim 1, wherein the charge carriers are electrons.

3. The method of claim 1, wherein the charge carriers are light-holes.

4. A method of operating a nonvolatile memory cell having a plurality of states, the memory cell comprising a strained tunneling gate, a strained ballistic gate disposed adjacent to and insulated from the strained tunneling gate, a storage region disposed adjacent to and insulated from the strained ballistic gate, a strain source providing a mechanical stress to the strained tunneling gate and the strained ballistic gate to provide a piezo-effect, and spaced-apart source and drain regions of a first conductivity type in a body of a semiconductor of a second conductivity type, the method comprising the steps of:

applying a first voltage to the strained tunneling gate;

applying a second voltage to the strained ballistic gate;

applying a body voltage to the body;

applying a source voltage to the source region; and

applying a drain voltage to the drain region to establish one of the plurality of states of the memory cell by injecting charge carriers from the strained tunneling gate through the strained ballistic gate into the storage region.

5. The method of claim 4, wherein the memory cell stores one of the plurality of states by storing a discrete amount of charges on the storage region.

6. The method of claim 4, wherein the body voltage, the source voltage, and the drain voltage are set at a first voltage setting to establish the memory cell in a first state of the plurality of states, and the method further comprises:

applying a second voltage setting to the body voltage, the source voltage, and the drain voltage to establish the memory cell in a second state of the plurality of states;

applying a third voltage setting to the body voltage, the source voltage, and the drain voltage to establish the memory cell in a third state of the plurality of states; and

applying a fourth voltage setting to the body voltage, the source voltage, and the drain voltage to establish the memory cell in a fourth state of the plurality of states.

7. The method of claim 6, wherein an amount of charges on the storage region in the first state is less than an amount of charges on the storage region in the second state, an amount of charges on the storage region in the second state is less than an amount of charges on the storage region in the third state, and an amount of charges on the storage region in the third state is less than an amount of charges on the storage region in the fourth state.

8. The method of claim 4, wherein the first voltage and the second voltage are set at a first voltage setting to establish the memory cell in a first state of the plurality of states, and the method further comprises:

applying a second voltage setting to the first voltage and the second voltage to establish the memory cell in a second state of the plurality of states;

applying a third voltage setting to the first voltage and the second voltage to establish the memory cell in third state of the plurality of states; and

applying a fourth voltage setting to the first voltage and the second voltage to establish the memory cell in a fourth state of the plurality of states.

9. The method of claim 8, wherein an amount of charges on the storage region in the first state is less than an amount of charges on the storage region in the second state, an amount of charges on the storage region in the second state is less than an amount of charges on the storage region in the third state, and an amount of charges on the storage region in the third state is less than an amount of charges on the storage region in the fourth state.

10. The method of claim 4. wherein the storage region comprises material selected from the group consisting of conductive material, nano-particles, and dielectrics.

11. The method of claim 4. wherein the charge carriers are electrons.

12. The method of claim 4. wherein the charge carriers are light- holes.

13. The method of claim 4, wherein the memory cell further comprises an injection filter permitting charge carriers of one polarity type transporting from the strained tunneling gate through the strained ballistic gate to the storage region and substantially blocking charge carriers of an opposite polarity type transporting from the strained ballistic gate to the strained tunneling gate.

14. The method of claim 13 wherein the injection filter has a barrier between the strained tunneling gate and the strained ballistic gate that has an entrance barrier height at an entrance and an exit barrier height at an exit for charge carriers traveling in a direction from the entrance to the exit, and

wherein said first voltage and said second voltage are applied to cause the entrance barrier height and the exit barrier height to be associated with at least one energy level that is greater than a carrier energy level for the charge carriers and the exit barrier height to be less than or equal to the entrance barrier height such that the barrier is trapezoidal-shaped.

15. The method of claim 14, wherein the memory cell further comprising a strain source providing a mechanical stress to at least one of the strained tunneling gate and the strained ballistic gate.

16. The method of claim 13 wherein the injection filter includes a blocking dielectric that has a band offset with respect to the strained tunneling gate.

17. The method of claim 16, wherein the charge carriers are electrons and the band offset is a conduction band offset, and wherein a magnitude of a voltage difference between the first and the second voltages is smaller than a sum of the conduction band offset and an energy band gap of the strained ballistic gate minus a flat-band voltage of the injection filter.

18. The method of claim 17, wherein the magnitude of the voltage difference is in a range of about 1 V to about 2 V.

19. The method of claim 16, wherein the charge carriers are holes and the band offset is a valence band offset, and wherein a voltage difference between the first and the second voltages is smaller than a sum of the valence band offset and a flat-band voltage of the injection filter.

20. The method of claim 19, wherein the voltage difference is in a range of about 2 V to about 2.5 V.