Shifting reference values to account for voltage sag

• US 7,613,043 B2
• Filed: 03/30/2007
• Issued: 11/03/2009
• Est. Priority Date: 05/15/2006
• Status: Expired due to Fees

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Cornwell, Michael J., Dudte, Christopher P.
• Primary Examiner(s): Zarabian; Amir
• Assistant Examiner(s): Hidalgo; Fernando N
• Application Number:
  US11/694,694
• Publication Number:
  US 20080013380A1
• Time in Patent Office: 949 Days
• Field of Search: 365/185.2, 365/185.21, 365/185.03, 365/185.08, 365/185.09, 365/185.12, 365/185.14, 365/185.17, 365/185.18, 365/185.19, 365/185.22, 365/185.24, 365/185.33
• US Class Current: 365/185.18
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Abstract

A system and method, including software implemented techniques, can be used to adjust for sag in stored data values. Charge is applied to multiple memory cells, and each memory cell is charged to a target voltage corresponding to a data value. The memory cells include a reference cell that is charged to a predetermined voltage. A voltage level in the reference cell is detected, and voltage levels from a group of memory cells are also detected. An adjustment is performed based upon the difference between the detected voltage level in the reference cell and the predetermined voltage.

Claims

1. A method for adjusting for sag in stored data values, the method comprising:

applying charge to a plurality of memory cells, each memory cell charged to a target voltage corresponding to a data value, the plurality of memory cells comprising a reference cell, the reference cell charged to a predetermined voltage;

detecting a voltage level in the reference cell;

detecting voltage levels from a group of memory cells;

performing an adjustment based upon the difference between the detected voltage level in the reference cell and the predetermined voltage, wherein the adjustment is an adjustment to a correction function, the correction function converting detected voltage levels into corrected voltage levels;

for each detected voltage level from the group of memory cells, receiving at a data processor a digital signal representing the detected voltage level;

applying the adjusted correction function in the data processor to convert the received digital signals representing the detected voltage levels from the group of memory cells into corrected digital signals representing corrected voltage levels; and

converting the corrected digital signals representing the corrected voltage levels into digital data values selected from a group of possible data values based upon a selection criteria.

2. The method of claim 1, wherein the plurality of memory cells comprise a page of memory cells, and wherein the page of memory cells comprise the group of memory cells.

3. The method of claim 2, wherein the page of memory cells comprises the reference cell.

4. The method of claim 1, wherein applying the adjusted correction function to convert the received digital signals representing the detected voltage levels from the group of memory cells into corrected voltage levels comprises:

converting analog signals representing the detected voltage levels into digital signals representing the detected voltage levels.

5. The method of claim 1, wherein the selection criteria relates each possible data value to one range of a plurality of non-overlapping ranges of voltages levels.

6. The method of claim 1, further comprising:

performing an error detection test; and

performing a second adjustment in response to a failure of the error detection test.

7. The method of claim 1, wherein the plurality of memory cells comprise NAND flash memory cells.

8. The method of claim 1, wherein the plurality of memory cells comprise NOR flash memory cells.

9. The method of claim 1, wherein each data value comprises more than 4 bits.

10. A system for reading data from memory cells, the system comprising:

a plurality of memory cells, each memory cell adapted to receive a charge to an analog voltage representing a data value selected from a group of possible data values, the plurality of memory cells comprising a reference cell charged to a predetermined voltage;

a voltage detector adapted to detect voltage levels for each memory cell; and

a processor adapted to adjust a correction function based in part upon a digital signal representing a detected voltage for the reference cell and a digital signal representing the predetermined voltage and to apply the adjusted correction function to convert digital signals representing detected voltage levels from the group of memory cells into corrected digital signals representing corrected voltage levels.

11. The system of claim 10, further comprising:

an analog-to-digital converter to convert analog signals representing the detected voltage levels into digital signals representing the detected voltage levels to allow for digital processing of each detected voltage level.

12. The system of claim 10, further comprising:

a set of memory cells associated with the group of memory cells, the set of memory cells adapted to store metadata to detect errors associated with the group of memory cells, wherein the processor is adapted to use the metadata to perform an error detection test.

13. The system of claim 12, wherein the metadata comprises error correction code contained in a page of memory cells, the set of memory cells and the plurality of memory cells contained in the page of memory cells.

14. An article of manufacture comprising machine-readable instructions that, when executed, cause operations to be performed, the operations comprising:

detecting voltage levels from a group of memory cells, the group of memory cells comprising a reference cell having a predetermined voltage;

performing an adjustment based upon the difference between the detected voltage level in the reference cell and the predetermined voltage, wherein the adjustment is an adjustment to a correction function, the correction function converting detected voltage levels into corrected voltage levels;

for each detected voltage level from the group of memory cells, receiving at a data processor a digital signal representing the detected voltage level;

applying the adjusted correction function in the data processor to convert the received digital signals representing the detected voltage levels from the group of memory cells into corrected digital signals representing corrected voltage levels; and

converting the corrected digital signals representing the corrected voltage levels into digital data values selected from a group of possible data values based upon a selection criteria.

15. The article of claim 14, the operations further comprising:

performing an error detection test on the digital data values for the group of memory cells.