Methods, circuits, and systems to select memory regions

• US 7,613,060 B2
• Filed: 05/21/2007
• Issued: 11/03/2009
• Est. Priority Date: 05/21/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Smith, Scott E.
• Primary Examiner(s): Zarabian; Amir
• Assistant Examiner(s): RADKE, JAY W
• Application Number:
  US11/805,092
• Publication Number:
  US 20080291765A1
• Time in Patent Office: 897 Days
• Field of Search: 365/222, 365/226, 365/227, 365/228, 711/5
• US Class Current: 365/222
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays
• CPC Class Codes: G11C 11/4082 Address Buffers; level conversion circuits
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Embodiments for selecting regions of memory are described. For example, in one embodiment a memory device having an array of memory cells includes an array selection block. The array selection block receives an input signal indicative of a region in the array of memory cells. The array selection block generates a selection signal to map the region to at least one physical location in the array of memory cells, based on the detection of the number of defects in that location.

Claims

1. A memory device comprising:

an array of memory cells; and

an array selection block in communication with the array of memory cells and configured to receive an address signal indicative of a location in the array of memory cells, the array selection block being operable to generate a selection signal responsive to the address signal that is indicative of at least one region of the array of memory cells, the array selection block being further operable to generate the selection signal on the basis of the number of defective cells that are replaced by redundant cells in the at least one region relative to that of at least one other region selectable by the array selection block.

2. The memory device of claim 1 further comprising a refresh control block in communication with the array selection block, the refresh control block operable to assign a region of the memory cells to be refreshed in response to the selection of a partial array self-refresh mode.

3. The memory device of claim 2 wherein the refresh control block further comprises an activate command logic module operable to generate a control signal to select only the addresses within the at least one region of the array of memory cells responsive to selecting the partial array self-refresh mode.

4. The memory device of claim 3, wherein the array selection block further comprises an activation module in communication with the activate command logic module, the activation module operable to enable a selection of the selected memory cells of the array responsive to receiving the control signal from the activate command logic module.

5. The memory device of claim 1 wherein the array of memory cells are partitioned into four regions.

6. A memory device having an array of memory cells, the memory device comprising:

an address register block configured to receive external address signals and operable to generate internal address signals corresponding to the external address signals; and

an array selection block in communication with the address register block and the array of memory cells, the array selection block configured to receive the internal address signals and an input signal indicative of the number of defective cells that are replaced by redundant cells in at least one region of memory cells selectable by the array selection block relative to that of at least one other region of memory cells selectable by the array selection block, and the array selection block operable to map the internal address signals to a physical location of the array of memory cells based on the input signal.

7. The memory device of claim 6 further comprising a refresh control block in communication with the address register block to receive the internal address signals, the refresh control block operable to generate a control signal to select the memory cells of address signals to be refreshed in a partial array self-refresh mode.

8. The memory device of claim 7 wherein the array selection block further comprises an activation module, the activation module operable to enable a selection of the selected memory cells of the array responsive to receiving the control signal from the refresh control block.

9. The memory device of claim 6 wherein the array selection block is operable to map the internal address signals to a physical location of the array of memory cells based on a refresh characteristic.

10. The memory device of claim 9 wherein the refresh characteristic comprise a time between refresh that is double the standard time between refresh.

11. A memory module comprising:

a plurality of memory devices; and

a memory hub configured to receive memory requests corresponding to a first region of memory devices, the memory hub operable to communicate the memory requests to the memory devices and transmit memory data from the memory devices in response to at least one of the memory requests; and

a selection block configured to receive the memory requests corresponding to the first region memory devices and to receive an input signal indicative of the number of defective cells that are replaced by redundant cells in at least one region of memory devices selectable by the selection block relative to that of at least another region of memory devices selectable by the selection block, the selection block operable to map the memory requests to a second region of memory devices based on the input signal.

12. The memory module of claim 11 wherein the second region of memory devices comprise a lower rate of defective memory cells that are detected relative to the first region of memory devices.

13. A processor-based system comprising:

a processor operable to process data and to provide memory commands and addresses;

a system controller in communication with the processor, the system controller operable to receive and transmit memory commands, addresses and data;

a plurality of memory devices in communication with the system controller, each of the plurality of memory devices operable to receive memory commands, addresses and write data for storage in at least one of the memory devices and to transmit read data from the memory devices to the system controller; and

a selection block configured to receive an address signal indicative of a region of memory devices, the selection block being operable to generate a selection signal to map the address signal indicative of the region of memory devices to a physical location of the plurality of memory devices, and the selection block being operable to generate the selection signal on the basis of the number of defective cells that are replaced by redundant cells in the physical location of the plurality of memory devices relative to that of at least one other region selectable by the selection block.