Semiconductor memory device in which data is stored in nonvolatile state, by using semiconductor elements of metal oxide semiconductor (MOS) structure

• US 7,613,062 B2
• Filed: 04/23/2007
• Issued: 11/03/2009
• Est. Priority Date: 07/03/2006
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ito, Hiroshi, Wada, Osamu, Namekawa, Toshimasa, Nakano, Hiroaki, Nakayama, Atsushi
• Primary Examiner(s): Ho; Hoai V
• Assistant Examiner(s): Hidalgo; Fernando N
• Application Number:
  US11/738,774
• Publication Number:
  US 20080002504A1
• Time in Patent Office: 925 Days
• Field of Search: 365/225.7, 365/189.19, 365/96
• US Class Current: 365/225.7
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor memory device includes a memory element, a first data line and a second data line, a first selection transistor, and a second selection transistor. The memory element includes a semiconductor element of MOS structure in which data is programmed when an insulating film provided in the semiconductor element is broken down by application of a voltage thereto. The first and second data lines are connected to a sense amplifier. The first selection transistor is configured to connect the memory element to the first data line in order to program data in the memory element. The second selection transistor is configured to connect the memory element to the second data line in order to program data in the memory element and detect the data programmed in the memory element. The second selection transistor has a smaller gate-electrode width smaller than the first selection transistor.

Claims

1. A semiconductor memory device comprising:

a first data line and a second data line connected to each of a plurality of sense amplifiers; and

a plurality of memory cells arranged in rows and columns, each of the memory cells including a memory element and first and second selection transistors,

wherein;

the memory element includes a semiconductor element of metal oxide semiconductor (MOS) structure, and data is programmed when an insulating film is broken down by application of a voltage;

the first selection transistor connects the memory element to the first data line in order to program data;

the second selection transistor connects the memory element to the second data line in order to program data and sense the programmed data, the second selection transistor having a gate-electrode width that is smaller than that of the first selection transistor; and

each of the memory cells further includes a first electric-field mitigating transistor connected between the memory element and the first and second selection transistors, a third selection transistor connected between the first selection transistor and the first data line, and a second electric-field mitigating transistor connected between the second selection transistor and the first electric-field mitigating transistor.

2. The semiconductor memory device according to claim 1, wherein the memory element is a low-voltage MOS transistor in which the insulating film has a first thickness;

and each of the first and second selection transistors is a high-voltage MOS transistor in which an insulating film has a second thickness greater than the first thickness.

3. The semiconductor memory device according to claim 2, wherein the low-voltage MOS transistor is a pMOS transistor.

4. The semiconductor memory device according to claim 2, wherein the high-voltage MOS transistor is an nMOS transistor.

5. The semiconductor memory device according to claim 1, wherein a row decoder applies a voltage to one end of the memory element in order to break down the insulating film.

6. The semiconductor memory device according to claim 1, wherein a voltage is applied directly to one end of memory element in order to break down an insulating film of the memory element.

7. The semiconductor memory device according to claim 1, wherein the memory element, the first selection transistor and the second selection transistor are low-voltage MOS transistors, each having an insulating film of a first thickness.

8. The semiconductor memory device according to claim 7, wherein the low-voltage MOS transistor included in the memory element is a pMOS transistor.

9. The semiconductor memory device according to claim 7, wherein the low-voltage MOS transistor which are the first and second selection transistors are nMOS transistors.

10. The semiconductor memory device according to claim 1, wherein a voltage is applied directly to one end of memory element in order to break down the insulating film of the memory element.

11. The semiconductor memory device according to claim 1, wherein the memory element, the first, second and third selection transistors and the first and second electric-field mitigating transistors are low-voltage MOS transistors, each having an insulating film of a first thickness.

12. The semiconductor memory device according to claim 11, wherein the low-voltage MOS transistors are nMOS transistors.