Systems, methods and computer program products for high speed data transfer using an external clock signal

• US 7,613,265 B2
• Filed: 09/05/2006
• Issued: 11/03/2009
• Est. Priority Date: 09/05/2006
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Campbell, John E.
• Primary Examiner(s): Bocure; Tesfaldet
• Application Number:
  US11/470,067
• Publication Number:
  US 20080059831A1
• Time in Patent Office: 1,155 Days
• Field of Search: 375371-373, 375/376, 375359-361, 365/233
• US Class Current: 375/360
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

Systems, methods and computer program products for capturing data. The methods include receiving an external clock signal having a first frequency, a first edge and a second edge. A clock period of the external clock period is the amount of time between any two successive first edges. The external clock signal is transformed into an internal clock signal based on the first edge and not the second edge of the external clock signal. Parallel data is received on a first plurality of signal links. The parallel data is received at a second frequency that is faster than the first frequency. The parallel data is captured using the internal clock signal.

Claims

1. A method for capturing data, the method comprising:

receiving an external clock signal having a first frequency, a first edge and a second edge, wherein a clock period of the external clock signal is the amount of time between any two successive first edges, and the external clock signal is received at an external clock port;

transforming the external clock signal into an internal clock signal based on the first edge and not the second edge of the external clock signal;

receiving parallel data at a first plurality of signal link ports, wherein the parallel data is received at a second frequency faster than the first frequency; and

capturing the received parallel data using the internal clock signal, wherein the internal clock signal consists of any one of a first internal clock signal running at the second frequency, a plurality of second internal clock signals running at the first frequency wherein each second internal clock signal comprises a pulse such that the combination of clock pulses of the plurality of second internal clock signals constitute said second frequency, or a plurality of clock signals running at the second frequency.

2. The method of claim 1 wherein the external clock signal consists of any one of the first edge is a rising edge and the second edge is a falling edge, or the first edge is a falling edge and the second edge is a rising edge.

3. The method of claim 1 wherein the parallel data comprises first data received at a first internal clock time during a first external period and second data received at a second internal clock time during the first external period.

4. The method of claim 3 wherein the first data comprises a plurality of bits of a single word of data.

5. The method of claim 3 wherein the first data comprises a plurality of bits including a first bit from a first link and a second bit from a second link, wherein data received at the second internal clock time comprises a plurality of bits including a third bit from the first link and a fourth bit from the second link, wherein the first bit and the third bit comprise bits of a first single word of data and wherein the second bit and the fourth bit comprise bits of a second single word of data.

6. The method of claim 1 wherein the transforming is performed by a phase-locked-loop circuit.

7. The method of claim 1 further comprising transmitting second parallel data on a second plurality of signal links, wherein the second parallel data is transmitted at the second frequency.

8. The method of claim 1 wherein the receiving an external clock signal, the transforming, the receiving parallel data and the capturing are performed at a memory device.

9. A system for capturing data, the system comprising:

an external clock port for receiving an external clock signal having a first frequency, a first edge and a second edge, wherein a clock period of the external clock signal is the amount of time between any two successive first edges;

a first plurality of signal link ports for receiving parallel data at a second frequency faster than the first frequency; and

logic in communication with the external clock port and the first plurality of signal link ports for facilitating;

transforming the external clock signal into an internal clock signal based on the first edge and not the second edge of the external clock signal, wherein the internal clock signal consists of any one of a first internal clock signal running at a second frequency, a plurality of second internal clock signals running at the first frequency wherein each second internal clock signal comprises a pulse such that the combination of clock pulses of the plurality of second internal clock signals constitute said second frequency, or a plurality of clock signals running at the second frequency; and

capturing the parallel data using the internal clock signal.

10. The system of claim 9 wherein the external clock port, the first plurality of signal link ports and the logic are located on a memory device.

11. The system of claim 10 wherein the internal clock signal is utilized to write the parallel data to the memory device and to read data stored on the memory device.

12. The system of claim 9 wherein the external clock port, the first plurality of signal link ports and the logic are located on a buffer device.

13. The system of claim 9 wherein the external clock port, the first plurality of signal link ports and the logic are located on a memory controller.

14. The system of claim 9 wherein the external clock signal consists of any one of the first edge is a rising edge and the second edge is a falling edge or the first edge is a falling edge and the second edge is a rising edge.

15. The system of claim 9 wherein the parallel data comprises first data received at a first internal clock time during a first external period and second data received at a second internal clock time during the first external period.

16. The system of claim 9 wherein the transforming is performed by a phase-locked-loop circuit.

17. The system of claim 9 wherein the logic further facilitates transmitting second parallel data via a second plurality of signal ports at the second frequency.

18. A service for deploying technology for high speed data transfer, the service comprising:

creating information for any one of making, using or selling technology for high speed data transfer, the technology including;

an external clock port for receiving an external clock signal having a first frequency, a first edge and a second edge, wherein a clock period of the external clock signal is the amount of time between any two successive first edges;

a first plurality of signal link ports for receiving parallel data at a second frequency faster than the first frequency; and

logic in communication with the external clock port and the first plurality of signal link ports for facilitating;

transforming the external clock signal into an internal clock signal based on the first edge and not the second edge of the external clock signal, wherein the internal clock signal consists of any one of a first internal clock signal running at the second frequency, a plurality of second internal clock signals running at the first frequency wherein each second internal clock signal comprises a pulse such that the combination of clock pulses of the plurality of second internal clock signals constitute said second frequency, or a plurality of clock signals running at the second frequency; and

capturing the parallel data using the internal clock signal; and

deploying said created information to one or more customers via a distribution process.

19. The service of claim 18, wherein the information comprises any one of circuit comprising the external clock port, the signal link ports and the logic, a design of the circuit, electrical characteristics of the circuit, or a design rule associated with the circuit, wherein the information is distributed in a tangible form consisting of any one of an ASIC chip die, a hard copy document, a soft copy electronic document, an electronic transmission or via portable media, the portable media comprising any one of a CD, a DVD, a magnetic tape, a magnetic disk, or a FLASH memory.

20. A buffer device in a memory system, the buffer device comprising:

an external clock port for receiving an external clock signal having a first frequency, a first edge, and a second edge, wherein a clock period of the external clock is the amount of time between any two successive first edges;

a first plurality of signal link ports for receiving parallel data at a second frequency faster than the first frequency; and

logic in communication with the external clock port and the first plurality of signal link ports for facilitating;

transforming the external clock signal into an internal clock signal based on the first edge and not the second edge of the external clock signal, wherein the internal clock signal consists of any one of a first internal clock signal running at the second frequency, a plurality of second internal clock signals running at the first frequency wherein each second internal clock signal comprises a pulse such that the combination of clock pulses of the plurality of second internal clock signals constitute said second frequency, or a plurality of clock signals running at the second frequency; and

capturing the parallel data using the internal clock signal.

21. The buffer device of claim 20 wherein the buffer device is in communication with a memory controller via a memory bus and the parallel data is received from the memory controller via the memory bus at the first frequency.

22. The buffer device of claim 20 wherein the buffer device is in communication with a memory device via a memory device interface and the parallel data is transferred to the memory device at the second frequency.

23. A computer program product for capturing data, the computer program product comprising:

a computer readable storage medium having instructions embodied thereon, which when executed by a computer, cause the computer to execute a method comprising;

receiving an external clock signal having a first frequency, a first edge and a second edge, wherein a clock period of the external clock signal is the amount of time between any two successive first edges;

transforming the external clock signal into an internal clock signal based on the first edge and not the second edge of the external clock signal;

receiving parallel data on a first plurality of signal links, wherein the parallel data is received at a second frequency faster than the first frequency; and

capturing the received parallel data using the internal clock signal, wherein the internal clock signal consists of any one of a first internal clock signal running at the second frequency, a plurality of second internal clock signals running at the first frequency wherein each second internal clock signal comprises a pulse such that the combination of clock pulses of the plurality of second internal clock signals constitute said second frequency, or a plurality of clock signals running at the second frequency.

24. The computer program product of claim 23 wherein the external clock signal consists of any one of the first edge is a rising edge and the second edge is a falling edge, or the first edge is a falling edge and the second edge is a rising edge.

25. The computer program product of claim 23 wherein the parallel data comprises first data received at a first internal clock time during a first external period and second data received at a second internal clock time during the first external period.

26. The computer program product of claim 25 wherein the first data comprises a plurality of bits of a single word of data.

27. The computer program product of claim 25 wherein the first data comprises a plurality of bits including a first bit from a first link and a second bit from a second link, wherein data received at the second internal clock time comprises a plurality of bits including a third bit from the first link and a fourth bit from the second link, wherein the first bit and the third bit comprise bits of a first single word of data and wherein the second bit and the fourth bit comprise bits of a second single word of data.

28. The computer program product of claim 23 wherein the method further compresses transmitting second parallel data on a second plurality of signal links, wherein the second parallel data is transmitted at the second frequency.

29. The computer program product of claim 23 wherein the receiving an external clock signal, the transforming, the receiving parallel data and the capturing are performed at a memory device.