Transceiver module and integrated circuit with dual eye openers and integrated loopback and bit error rate testing
First Claim
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1. An integrated circuit for use in a transceiver module, the integrated circuit comprising:
- a first electrical input port for receiving a first serial electrical data stream;
receiver eye opener circuitry including components for retiming and reshaping the first serial electrical data stream, the components including a clock and data recovery, an equalizer, and a coefficient module, wherein the equalizer used a clock from the clock and data recovery and coefficients generated by the coefficient module to condition the first serial electrical data stream;
a first electrical output port for transmitting the retimed and reshaped first serial electrical data stream to external to the integrated circuit;
a second electrical input port for receiving a second serial electrical data stream from external to the integrated circuit;
transmitter eye opener circuitry including components for retiming and reshaping the second serial electrical data stream;
a second electrical output port for transmitting the retimed and reshaped second serial electrical data stream; and
a bit error rate tester (BERT) engine for testing a test data path from a starting test point to an ending test point, the starting test point and the ending test point each located on either a receive path or on a transmit path, wherein the receive path is from the first electrical input port through the receiver eye opener circuitry to the first electrical output port and the transmit path is from the second electrical input port through the transmitter eye opener circuitry to the second electrical output port.
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Abstract
A transceiver module having integrated eye diagram opening functionality for reducing jitter is described. The transceiver module may include a transmitter eye opener and a receiver eye opener integrated in single circuit. The transceiver module may also include serial control and various other integrated components. Other functionalities that may be integrated on the transceiver module include loopback modules, bypass features, bit error rate testing, and power down modes.
182 Citations
11 Claims
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1. An integrated circuit for use in a transceiver module, the integrated circuit comprising:
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a first electrical input port for receiving a first serial electrical data stream; receiver eye opener circuitry including components for retiming and reshaping the first serial electrical data stream, the components including a clock and data recovery, an equalizer, and a coefficient module, wherein the equalizer used a clock from the clock and data recovery and coefficients generated by the coefficient module to condition the first serial electrical data stream; a first electrical output port for transmitting the retimed and reshaped first serial electrical data stream to external to the integrated circuit; a second electrical input port for receiving a second serial electrical data stream from external to the integrated circuit; transmitter eye opener circuitry including components for retiming and reshaping the second serial electrical data stream; a second electrical output port for transmitting the retimed and reshaped second serial electrical data stream; and a bit error rate tester (BERT) engine for testing a test data path from a starting test point to an ending test point, the starting test point and the ending test point each located on either a receive path or on a transmit path, wherein the receive path is from the first electrical input port through the receiver eye opener circuitry to the first electrical output port and the transmit path is from the second electrical input port through the transmitter eye opener circuitry to the second electrical output port. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An integrated circuit for use in a transceiver module, the integrated circuit comprising:
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first input means for receiving a first serial electrical data stream; first eye opener means for retiming and reshaping the first serial electrical data stream; first output means for transmitting the retimed and reshaped first serial electrical data stream to external to the integrated circuit; second input means for receiving a second serial electrical data stream from external to the integrated circuit; second eye opener means for retiming and reshaping the second serial electrical data stream, wherein the second eye opener means further conditions the second serial electrical signal using an equalizer and a clock and data recovery; second output means for transmitting the retimed and reshaped second serial electrical data stream; and BERT testing means for testing a test data path from a starting test point to an ending test point, the starting test point and the ending test point each located on either a receive path or on a transmit path, wherein the receive path is from the first input means through the first eye opener means to the first output means and the transmit path is from the second input means through the second eye opener means to the second output means.
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Specification