Efficient implementation of multi-channel integrators and differentiators in a programmable device

• US 7,613,760 B1
• Filed: 03/18/2004
• Issued: 11/03/2009
• Est. Priority Date: 03/18/2004
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Moore, David J., Esposito, Benjamin J.
• Primary Examiner(s): Bullock, Jr.; Lewis A
• Assistant Examiner(s): YAARY, MICHAEL D
• Application Number:
  US10/804,294
• Time in Patent Office: 2,056 Days
• Field of Search: 708/313
• US Class Current: 708/313
• CPC Class Codes: H03H 17/0223 Computation saving measures; Accelerating measures computations per se G06F
• CPC Class Codes: H03H 17/0664 where the output-delivery frequency is lower than the input sampling frequency, i.e. decimation
• CPC Class Codes: H03H 17/0671 Cascaded integrator-comb [CIC] filters
• CPC Class Codes: H03H 2218/08 Resource sharing

Abstract

Efficiently implemented multi-channel integrators and multi-channel differentiators utilize a delay section in a single integrator or differentiator in lieu of parallel integrator or differentiator lines to handle multi-channel data flow and processing. The delay section functions like a shift register, greatly reducing the space and/or resources required for implementing the integrator or differentiator. Such integrators and differentiators can be used in multi-channel decimators, interpolators and numerically controlled oscillators in place of multiple instances of single channel integrators that have had to be used in earlier systems. These structures and devices can be implemented in programmable devices such as PLDs and similar devices, in which the delay section can be implemented in embedded memory in the device. Multi-stage decimators and interpolators can use multiple instances of an integrator and/or differentiator in series.

Claims

1. A multi-channel integrator comprising:

an integrator input;

an integrator output;

an adder comprising;

a first adder input connected to the integrator input;

a second adder input; and

an adder output;

a delay section comprising;

a delay section input that receives data of a plurality of channels;

a delay section output; and

a plurality of delay elements connected in series between the delay section input and the delay section output, each delay element of the plurality of delay elements delaying the data of each of the plurality of channels and providing an output that is specific to an individual channel of the plurality of channels; and

a feedback line connecting the delay section output to the second adder input;

wherein the adder output is connected to the delay section input; and

further wherein the delay section output is connected to the integrator output.

2. A multi-channel numerically controlled oscillator comprising the integrator of claim 1.

3. The multi-channel numerically controlled oscillator of claim 2 further comprising:

a phase incrementer input multiplexer connected to the integrator input; and

a sine/cosine generation unit connected to the integrator output.

4. The multi-channel numerically controlled oscillator of claim 2 wherein the numerically controlled oscillator is an M channel numerically controlled oscillator and further wherein the delay section of the integrator comprises at least M delay elements in series.

5. An M channel decimator, wherein M>

1, the decimator comprising;

the integrator of claim 1.

6. The M channel decimator of claim 5 further comprising:

a down-sampler having a down-sampler input connected to the integrator output and a down-sampler output;

a differentiator connected to the down-sampler output; and

a multiplexer that multiplexes M channels and provides a multiplexed signal to the integrator.

7. An N stage multi-channel decimator wherein the decimator comprises an integrator section comprising at least N instances of the integrator of claim 1 in series.

8. The N stage multi-channel decimator of claim 7 wherein the decimator is an M channel decimator and further wherein the plurality of delay elements in each integrator comprises at least M delay elements.

9. An M channel interpolator, wherein M>

1, the interpolator comprising;

the integrator of claim 1 wherein the plurality of delay elements comprises at least M delay elements.

10. The M channel interpolator of claim 9 further comprising:

an up-sampler having an up-sampler output connected to the integrator input and an up-sampler input; and

a differentiator connected to the up-sampler input.

11. An N stage multi-channel interpolator wherein the interpolator comprises an integrator section comprising at least N instances of the integrator of claim 1 in series.

12. The N stage multi-channel interpolator of claim 11 wherein the interpolator is an M channel interpolator and further wherein each integrator in the integrator section comprises the integrator of claim 1 and further wherein the plurality of delay elements comprises at least M delay elements.

13. The integrator of claim 1 wherein the integrator is implemented in a programmable device.

14. The integrator of claim 1 wherein the delay section is implemented in one or more embedded memory blocks in a programmable device.

15. A multi-channel differentiator comprising:

a differentiator input;

a differentiator output;

a subtractor comprising;

a first subtractor input;

a second subtractor input; and

a subtractor output;

a delay section comprising;

a delay section input connected to the differentiator input, the delay section input receiving data of a plurality of channels;

a delay section output; and

a plurality of delay elements connected in series between the delay section input and the delay section output, each delay element of the plurality of delay elements delaying the data of each of the plurality of channels and providing an output that is specific to an individual channel of the plurality of channels; and

a feedforward line connecting the differentiator input to the first subtractor input;

wherein the delay section output is connected to the second subtractor input; and

wherein the subtractor output is connected to the differentiator output.

16. An M channel decimator, wherein M>

1, the decimator comprising;

the differentiator of claim 15 wherein the plurality of delay elements comprises at least M delay elements.

17. The M channel decimator of claim 16 further comprising:

a down-sampler having a down-sampler output connected to the differentiator input and a down-sampler input; and

an integrator connected to the down-sampler input.

18. An N stage multi-channel decimator wherein the decimator comprises a differentiator section comprising at least N instances of the differentiator of claim 15 in series.

19. The N stage multi-channel decimator of claim 18 wherein the decimator is an M channel decimator and further wherein the plurality of delay elements in each differentiator comprises at least M delay elements.

20. An M channel interpolator, wherein M>

1, the interpolator comprising;

the differentiator of claim 15 wherein the plurality of delay elements comprises at least M delay elements.

21. The M channel interpolator of claim 20 further comprising:

an up-sampler having an up-sampler input connected to the differentiator output and an up-sampler output; and

an integrator connected to the up-sampler output.

22. An N stage multi-channel interpolator wherein the interpolator comprises a differentiator section comprising at least N instances of the differentiator of claim 15 in series.

23. The N stage multi-channel interpolator of claim 22 wherein the interpolator is an M channel interpolator and further wherein the plurality of delay elements in each differentiator comprises at least M delay elements.

24. The differentiator of claim 15 wherein the integrator is implemented in a programmable device.

25. The differentiator of claim 15 wherein the delay section is implemented in one or more embedded memory blocks in a programmable device.

26. An N stage, M channel decimator, where M>

1, the decimator comprising;

an integrator section comprising;

an integrator section input comprising a multiplexer comprising M multiplexer inputs and a multiplexer output;

an integrator section output; and

N integrators connected in series between the integrator section input and the integrator output, wherein each integrator comprises;

an integrator input;

an integrator output;

an adder comprising;

a first adder input connected to the integrator input;

a second adder input; and

an adder output;

a delay section comprising;

a delay section input;

a delay section output; and

M delay elements connected in series between the delay section input and the delay section output, each of the M delay elements delaying data of each of the M multiplexer inputs and providing an output that is specific to an individual channel of the M channels; and

a feedback line connecting the delay section output to the second adder input;

wherein the adder output is connected to the delay section input; and

further wherein the delay section output is connected to the integrator output;

a differentiator section comprising;

a differentiator section input;

a differentiator output; and

N differentiators connected in series between the differentiator input and the differentiator output, wherein each differentiator comprises;

a differentiator input;

a differentiator output;

a subtractor comprising;

a first subtractor input;

a second subtractor input; and

a subtractor output;

a delay section comprising;

a delay section input connected to the differentiator input;

a delay section output; and

M delay elements connected in series between the delay section input and the delay section output; and

a feedforward line connecting the differentiator input to the first subtractor input;

wherein the delay section output is connected to the second subtractor input; and

wherein the subtractor output is connected to the differentiator output; and

a down-sampler comprising a down-sampler input connected to the integrator section output and a down-sampler output connected to the differentiator section input.

27. An N stage, M channel interpolator, where M>

1, the interpolator comprising;

a differentiator section comprising;

a differentiator section input comprising a multiplexer comprising M multiplexer inputs and a multiplexer output;

a differentiator output; and

N differentiators connected in series between the differentiator input and the differentiator output, wherein each differentiator comprises;

a differentiator input;

a differentiator output;

a subtractor comprising;

a first subtractor input;

a second subtractor input; and

a subtractor output;

a delay section comprising;

a delay section input connected to the differentiator input;

a delay section output; and

M delay elements connected in series between the delay section input and the delay section output, each of the M delay elements delaying data of each of the M multiplexer inputs and providing an output that is specific to an individual channel of the M channels; and

a feedforward line connecting the differentiator input to the first subtractor input;

wherein the delay section output is connected to the second subtractor input; and

wherein the subtractor output is connected to the differentiator output;

an integrator section comprising;

an integrator section input;

an integrator section output; and

N integrators connected in series between the integrator section input and the integrator output, wherein each integrator comprises;

an integrator input;

an integrator output;

an adder comprising;

a first adder input connected to the integrator input;

a second adder input; and

an adder output;

a delay section comprising;

a delay section input;

a delay section output; and

M delay elements connected in series between the delay section input and the delay section output; and

a feedback line connecting the delay section output to the second adder input;

wherein the adder output is connected to the delay section input; and

further wherein the delay section output is connected to the integrator output; and

an up-sampler comprising an up-sampler input connected to the differentiator section output and an up-sampler output connected to the integrator section input.

28. An M channel numerically controlled oscillator, where M>

1, the numerically controlled oscillator comprising;

an oscillator input comprising a multiplexer comprising M multiplexer inputs and a multiplexer output;

a sine/cosine generator having a generator input; and

an integrator comprising;

an integrator input connected to the multiplexer output;

an integrator output connected to the generator input;

an adder comprising;

a first adder input connected to the integrator input;

a second adder input; and

an adder output;

a delay section comprising;

a delay section input;

a delay section output; and

M delay elements connected in series between the delay section input and the delay section output, each of the M delay elements delaying data of each of the M multiplexer inputs and providing an output that is specific to an individual channel of the M channels; and

a feedback line connecting the delay section output to the second adder input;

wherein the adder output is connected to the delay section input; and

further wherein the delay section output is connected to the integrator output.

29. A computer program product for performing multi-channel integration on data of a plurality of channels, the computer program product stored on a computer storage media having computer readable code embodied therein, the computer readable code comprising:

computer code that, when executed by a processor, programs a device to create a programmed device, wherein the programmed device comprises;

a multi-channel integrator comprising;

an integrator input;

an integrator output;

an adder comprising;

a first adder input connected to the integrator input;

a second adder input; and

an adder output;

a delay section comprising;

a delay section input;

a delay section output; and

a plurality of delay elements connected in series between the delay section input and the delay section output, each delay element of the plurality of delay elements delaying the data of each of the plurality of channels and providing an output that is specific to an individual channel of the plurality of channels; and

a feedback line connecting the delay section output to the second adder input;

wherein the adder output is connected to the delay section input; and

furrther wherein the delay section output is connected to the integrator output.

30. A computer program product for performing multi-channel differentiation on data of a plurality of channels, the computer program product stored on a computer storage media having

computer readable code embodied therein, the computer readable code comprising:

computer code that, when executed by a processor, programs a device to create a programmed device, wherein the programmed device comprises;

a multi-channel differentiator comprising multi-channel differentiator comprising;

a differentiator input;

a differentiator output;

a subtractor comprising;

a first subtractor input;

a second subtractor input; and

a subtractor output;

a delay section comprising;

a delay section input connected to the differentiator input;

a delay section output; and

a plurality of delay elements connected in series between the delay section input and the delay section output, each delay element of the plurality of delay elements delaying the data of each of the plurality of channels and providing an output that is specific to an individual channel of the plurality of channels; and

a feedforward line connecting the differentiator input to the first subtractor input;

wherein the delay section output is connected to the second subtractor input; and

wherein the subtractor output is connected to the differentiator output.