Hybrid multi-tiered caching storage system

• US 7,613,876 B2
• Filed: 06/08/2006
• Issued: 11/03/2009
• Est. Priority Date: 06/08/2006
• Status: Active Grant

• Current Assignee: BiTMICRO, LLC (BiTMICRO Networks, Inc.)
• Original Assignee: BiTMICRO Networks, Inc.
• Inventors: Mateo, Noeme Paz, Bruce, Rey H., Nite, Ricky Sevilla
• Primary Examiner(s): Chace, Christian P
• Assistant Examiner(s): Farrokh, Hashem
• Application Number:
  US11/450,023
• Publication Number:
  US 20070288692A1
• Time in Patent Office: 1,244 Days
• Field of Search: 711/113, 711/203, 710/22
• US Class Current: 711/113
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/217 Hybrid disk, e.g. using both magnetic and solid state storage devices
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays

Abstract

A hybrid storage system comprising mechanical disk drive means, flash memory means, SDRAM memory means, and SRAM memory means is described. IO processor means and DMA controller means are devised to eliminate host intervention. Multi-tiered caching system and novel data structure for mapping logical address to physical address results in a configurable and scalable high performance computer data storage solution.

Claims

1. A data storage system for storing and retrieving computer data using one or more logical address without intervention from the external host or client system, the data storage system comprising:

an IO processor for controlling data input or output of a data storage system;

disk drive for storing one or more blocks of data, including data transferred from the host and control data for the IO processor;

a non-volatile memory means for storing a plurality of data blocks, the data blocks including data transferred from the host, a cached portion of data stored in the disk drive and control data for use by the IO processor;

a LBA Flash HDD first table for storing at least one logical address mapped to at least one physical address of said non-volatile memory means and at least one physical address of said disk drive;

wherein the LBA Flash HDD table enables memory access to said non-volatile memory means without intervention from the host;

a FAST memory means for storing one or more blocks of data, the data including data transferred from the host, a cached portion of data stored in the non-volatile memory means and control data for the IO processor means; and

a LBA_FAST table wherein at least one of the one or more logical addresses is searched in the LBA_FAST table and if found, the logical address is mapped to at least one FAST memory address, providing an association between the logical address and a physical location of data and enabling access to the data without intervention from the host.

2. The data storage system of claim 1 wherein the LBA_Flash_HDD table is updated from time to time according to a data access behavior pattern of the host computer without the host system intervention.

3. The data storage system of claim 1, wherein the LBA_FAST table and the LBA_Flash_HDD table are updated from time to time according to a data access behavior pattern of the host without intervention from the host.

4. The data storage system of claim 3, wherein the FAST memory means includes:

a SDRAM memory for storing one or more blocks of data, including data transferred from the host, a cached portion of data stored in the non-volatile memory means, control data for the IO processor, and the LBA_FAST table;

SRAM memory for storing one or more blocks of data, including control data for the IO processor, and for caching the LBA_FAST table; and

wherein, during operation, the LBA_Flash_HDD table is stored in the non-volatile-memory means and cached in the FAST memory means, a first cached portion is stored in the SRAM memory and a second cached portion containing the remainder of the LBA_Flash_HDD table is stored in the SDRAM memory and copy of the LBA_Flash_HDD table is stored in the disk drive.

5. The data storage system of claim 4 further, comprising:

a SDRAM DMA controller for transferring data to or from the SDRAM memory, the SDRAM DMA controller responsive to at least one DMA instruction;

a non-volatile DMA controller for transferring data to and from the non-volatile memory means, the non-volatile DMA controller responsive to at least one DMA instruction;

the IO processor for preparing at least one DMA instruction, the IO processor using the LBA_FAST table and the LBA_Flash_HDD table for mapping the one or more logical addresses; and

wherein the control data stored in the FAST memory means further includes at least one DMA instruction.

6. The data storage system of claim 4, further comprising:

a host DMA controller for transferring data to or from the host, the host DMA controller responsive to at least one DMA instruction and for interfacing the host with the data storage system;

CAM memory means for storing a byte address look up table wherein the host DMA controller transfers data to and from the host without the IO processor preparing the DMA instruction if the byte address look-up table contains a valid entry for the data requested by the host; and

an IO DMA controller for transferring data to and from the disk drive in response to at least one DMA instruction;

wherein the disk drives is coupled to the IO DMA controller via an IO interface.

7. The data storage system of claim 4, further comprising:

a first IO DMA controller for transferring data to and from the host computer in response to at least one DMA instruction;

a second IO DMA controller for transferring data to and from the disk drive in response to at least one DMA instruction;

wherein the host is coupled to the first IO DMA controller; and

wherein the disk drives is coupled to the second IO DMA controller.

8. The data storage system of claim 4 further comprising:

an IO DMA controller means for transferring data to and from the host in response to at least one DMA instruction; and

an external bus interface DMA controller means for transferring data to and from the disk drive in response to at least one DMA instruction;

wherein the host is coupled to the IO DMA controller means; and

wherein the disk drives is coupled to the external bus interface DMA controller means.

9. A data structure for storing mapping information of a data storage system, the data storage system comprising flash memory, SDRAM memory, and SRAM memory, the data structure comprising:

a LBA_Flash_HDD table comprising one or more logical address, one or more corresponding flash address, and one or more corresponding disk drive address; and

a LBA_SDRAM table comprising one or more logical address, one or more corresponding SRAM address, and one or more corresponding SDRAM address;

wherein a first portion of a working copy of the LBA_Flash_HDD table is stored in the SRAM memory, a second portion of the working copy is stored in the SDRAM memory; and

wherein the LBA_SDRAM table is stored in the SDRAM memory, and a cached portion of the LBA_SDRAM table is stored in the SRAM memory means.

10. A data storage system for performing memory operations on a mass storage unit in response to a host request received from a host, the data storage system comprising:

a means for processing program code in response to the host request, said means including an IO processor;

a first non-volatile memory DMA controller electrically coupled to said IO processor;

a first non-volatile memory electrically coupled to said first non-volatile DMA controller and for storing a first table and selected data transferred from the host, said first table for storing a plurality of logical addresses respectively mapped to at least one physical memory address;

program code for mapping a first logical address to a physical address of a first data location in said first non-volatile memory;

wherein, without requiring host intervention, said means for processing uses said first table when performing a memory operation on said first non-volatile memory;

a mass storage DMA controller electrically coupled to said IO processor and for electrically coupling to the mass storage unit;

wherein said program code for further mapping said first logical address to a physical address of a second data location in the mass storage unit;

a first volatile memory and a first volatile memory DMA controller electrically coupled to said first volatile memory and to said IO processor;

wherein the mass storage unit includes at least one hard disk drive;

wherein said first volatile memory for caching a portion of said selected data stored in said first non-volatile memory;

a second table for storing a plurality of logical addresses that are each respectively mapped to at least one physical address, said plurality of logical addresses including a second logical address mapped to a physical address of a third data location in said first volatile memory; and

wherein said means for processing uses selected contents of said second table when performing a memory operation on said first volatile memory.

11. A data storage system for performing memory operations on a mass storage unit in response to a host request received from a host, the data storage system comprising:

a means for processing program code in response to the host request, said means including an IO processor;

a first non-volatile memory DMA controller electrically coupled to said IO processor;

a first non-volatile memory electrically coupled to said first non-volatile DMA controller and for storing a first table and selected data transferred from the host, said first table for storing a plurality of logical addresses respectively mapped to at least one physical memory address;

program code for mapping a first logical address to a physical address of a first data location in said first non-volatile memory;

wherein, without requiring host intervention, said means for processing uses said first table when performing a memory operation on said first non-volatile memory;

a mass storage DMA controller electrically coupled to said IO processor and for electrically coupling to the mass storage unit;

wherein said program code for further mapping said first logical address to a physical address of a second data location in the mass storage unit;

a second volatile memory; and

wherein said first volatile memory for storing said second table, said second volatile memory for caching at least a portion of said second table; and

said second volatile memory includes SRAM.

12. A data storage system for performing memory operations on a mass storage unit in response to a host request received from a host, the data storage system comprising:

a means for processing program code in response to the host request, said means including an IO processor;

a first non-volatile memory DMA controller electrically coupled to said IO processor;

a first non-volatile memory electrically coupled to said first non-volatile DMA controller and for storing a first table and selected data transferred from the host, said first table for storing a plurality of logical addresses respectively mapped to at least one physical memory address;

program code for mapping a first logical address to a physical address of a first data location in said first non-volatile memory;

wherein, without requiring host intervention, said means for processing uses said first table when performing a memory operation on said first non-volatile memory;

a mass storage DMA controller electrically coupled to said IO processor and for electrically coupling to the mass storage unit;

wherein said program code for further mapping said first logical address to a physical address of a second data location in the mass storage unit; and

a program code for storing a copy of said first table in said mass storage unit in response to a selected event and said means for processing further includes a scratch pad buffer.

13. A data storage system for performing memory operations on a mass storage unit in response to a host request received from a host, the data storage system comprising:

a means for processing program code in response to the host request, said means including an IO processor;

a first non-volatile memory DMA controller electrically coupled to said IO processor;

a first non-volatile memory electrically coupled to said first non-volatile DMA controller and for storing a first table and selected data transferred from the host, said first table for storing a plurality of logical addresses respectively mapped to at least one physical memory address;

program code for mapping a first logical address to a physical address of a first data location in said first non-volatile memory;

wherein, without requiring host intervention, said means for processing uses said first table when performing a memory operation on said first non-volatile memory;

a mass storage DMA controller electrically coupled to said IO processor and for electrically coupling to the mass storage unit;

wherein said program code for further mapping said first logical address to a physical address of a second data location in the mass storage unit;

a host DMA controller for transferring data to or from the host in response to one or more DMA instructions;

a CAM for storing a byte address look up table, and in response to the byte address look-up table containing a valid entry for data requested by the host, said host DMA controller transfers data to and from the host without the IO processor preparing the DMA instruction; and

an IO storage DMA controller for transferring data to and from the mass storage unit in response to one or more DMA instructions and through an I/O interface.

14. A data storage system for performing memory operations on a mass storage unit in response to a host request received from a host, the data storage system comprising:

a means for processing program code in response to the host request, said means including an IO processor;

a first non-volatile memory DMA controller electrically coupled to said IO processor;

a first non-volatile memory electrically coupled to said first non-volatile DMA controller and for storing a first table and selected data transferred from the host, said first table for storing a plurality of logical addresses respectively mapped to at least one physical memory address;

program code for mapping a first logical address to a physical address of a first data location in said first non-volatile memory;

wherein, without requiring host intervention, said means for processing uses said first table when performing a memory operation on said first non-volatile memory;

wherein said IO processor creates a link of DMA instructions in response to said host request; and

wherein said first non-volatile memory DMA controller uses said link of DMA instructions to transfer information to or from said first non-volatile memory.

15. A data storage system for performing memory operations on a mass storage unit in response to a host request received from a host, the data storage system comprising:

a means for processing program code in response to the host request, said means including an IO processor;

a first non-volatile memory DMA controller electrically coupled to said IO processor;

a first non-volatile memory electrically coupled to said first non-volatile DMA controller and for storing a first table and selected data transferred from the host, said first table for storing a plurality of logical addresses respectively mapped to at least one physical memory address;

program code for mapping a first logical address to a physical address of a first data location in said first non-volatile memory;

wherein, without requiring host intervention, said means for processing uses said first table when performing a memory operation on said first non-volatile memory;

a mass storage DMA controller electrically coupled to said IO processor and for electrically coupling to the mass storage unit;

wherein said program code for further mapping said first logical address to a physical address of a second data location in the mass storage unit;

a second non-volatile DMA controller electrically coupled to said IO processor and for coupling to a second non-volatile memory; and

wherein said program code for further mapping said first logical address to a physical address of a second data location defined in said second non-volatile memory.

16. The data storage system of claim 15, further including:

a first volatile memory and a first volatile memory DMA controller electrically coupled to said first volatile memory and to said IO processor; and

wherein the mass storage unit includes at least one hard disk drive.

17. The data storage system of claim 15, wherein said means for processing uses selected contents of said first table when performing a memory operation on said mass storage unit.

18. The data storage system of claim 17, wherein said selected contents of said first table include said plurality of logical addresses respectively mapped to at least one physical address.

19. The data storage system of claim 15 further comprising:

a first IO means for transferring data to and from the host in response to at least one DMA instruction, said first IO means for interfacing with the host; and

a second IO means for transferring data to and from the mass storage unit in response to at least one DMA instruction, said second IO means for interfacing with the mass storage unit.

20. The data storage system of claim 19, wherein said first and second IO means respectively include a DMA controller.

21. The data storage system of claim 15, wherein said first non-volatile memory includes a flash memory, and said second non-volatile memory includes a hard disk drive;

and

wherein said program code for further mapping said first logical address to a physical address of a second data location defined in said second non-volatile memory.

22. The data storage system of claim 15, further including a first volatile memory.

23. The data storage system of claim 22, further including a first volatile memory controller and wherein said first volatile memory includes at least one SRAM.

24. The data storage system of claim 23, further including:

a bus;

said first volatile memory controller electrically coupled to said IO processor through said bus; and

wherein said first volatile memory includes at least one DRAM and is coupled to said bus.

25. The data storage system of claim 23, further including a read only memory.