Inversion of scan clock for scan cells

• US 7,613,967 B1
• Filed: 10/29/2008
• Issued: 11/03/2009
• Est. Priority Date: 07/29/2004
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Tan, Teck Wee Patrick
• Primary Examiner(s): Tabone, Jr.; John J
• Application Number:
  US12/290,262
• Time in Patent Office: 370 Days
• Field of Search: 714/726, 714/729, 714/731
• US Class Current: 714/726
• CPC Class Codes: G01R 31/318541 Scan latches or cell details
• CPC Class Codes: G01R 31/318594 Timing aspects clock circuits G01R31/318552

Abstract

A device includes a scan circuit including a scan chain. The scan chain includes a first plurality of scan cells that receive a first scan clock signal in a first clock domain. A second plurality of scan cells receives a second scan clock signal in a second clock domain. A scan clock source generates the first scan clock signal and the second scan clock signal, and selectively inverts the first scan clock signal and the second scan clock signal based on an operating mode of the first plurality of scan cells and the second plurality of scan cells, respective flip-flop arrangements of the first clock domain and the second clock domain.

Claims

1. A device comprising:

a scan circuit including a scan chain, the scan chain having

a first plurality of scan cells that receive a first scan clock signal in a first clock domain; and

a second plurality of scan cells that receive a second scan clock signal in a second clock domain; and

a scan clock source that generates the first scan clock signal and the second scan clock signal, and that selectively inverts the first scan clock signal and the second scan clock signal based on

an operating mode of the first plurality of scan cells and the second plurality of scan cells; and

respective flip-flop arrangements of the first clock domain and the second clock domain.

2. The device of claim 1, wherein a last scan cell of the first plurality of scan cells is directly connected to a first scan cell of the second plurality of scan cells.

3. The device of claim 1, wherein:

each scan cell of the first plurality of scan cells and the second pluralities of scan cells includes a flip-flop; and

each flip-flop in the second plurality of scan cells is triggered before any flip-flop in the first plurality of scan cells.

4. The device of claim 1, wherein:

a first scan cell in the first clock domain receives a scan-in signal based on the first scan clock signal; and

a last scan cell in the second clock domain generates a scan-out signal based on the second scan clock signal.

5. The device of claim 1, wherein the scan clock source receives an external clock signal and generates the first scan clock signal and the second scan clock signal based on the external clock signal.

6. The device of claim 5, wherein:

each scan cell of the first plurality of scan cells and the second plurality of scan cells includes a positive edge-triggered flip-flop; and

the first scan clock signal is inverted relative to the external clock signal.

7. The device of claim 5, wherein:

each scan cell of the first plurality of scan cells and the second plurality of scan cells includes a negative edge-triggered flip-flop; and

the second scan clock signal is inverted relative to the external clock signal.

8. The device of claim 1, wherein the scan circuit comprises a plurality of the scan chains.

9. An integrated circuit (IC) comprising the device of claim 1.

10. A method comprising:

receiving a first scan clock signal at a first plurality of scan cells in a first clock domain;

receiving a second scan clock signal at a second plurality of scan cells in a second clock domain;

generating the first scan clock signal and the second scan clock signal at a scan clock source; and

selectively inverting the first scan clock signal and the second scan clock signal based on

an operating mode of the first plurality of scan cells and the second plurality of scan cells; and

respective flip-flop arrangements of the first and second clock domains.

11. The method of claim 10, further comprising directly connecting a last scan cell of the first plurality of scan cells to a first scan cell of the second plurality of scan cells.

12. The method of claim 10, wherein:

each scan cell of the first plurality of scan cells and the second plurality of scan cells includes a flip-flop; and

each flip-flop in the second plurality of scan cells is triggered before any flip-flop in the first plurality of scan cells.

13. The method of claim 10, further comprising:

receiving a scan-in signal at a first scan cell in the first clock domain based on the first scan clock signal; and

generating a scan-out signal at a last scan cell in the second clock domain based on the second scan clock signal.

14. The method of claim 10, further comprising:

receiving an external clock signal; and

generating the first scan clock signal and the second scan clock signal based on the external clock signal.

15. The method of claim 14, wherein:

each scan cell of the first plurality of scan cells and the second plurality of scan cells includes a positive edge-triggered flip-flop; and

the first scan clock signal is inverted relative to the external clock signal.

16. The method of claim 14, wherein:

each scan cell of the first plurality of scan cells and the second plurality of scan cells includes a negative edge-triggered flip-flop; and

the second scan clock signal is inverted relative to the external clock signal.