Hierarchical trellis coded modulation

• US 7,613,985 B2
• Filed: 10/22/2004
• Issued: 11/03/2009
• Est. Priority Date: 10/24/2003
• Status: Active Grant

• Current Assignee: Ikanos Communications Incorporated (Qualcomm, Inc.)
• Original Assignee: Ikanos Communications Incorporated (Qualcomm, Inc.)
• Inventors: Moreno, Oliver, Duvaut, Patrick, Pons, Julien, Pierrugues, Laurent
• Primary Examiner(s): Torres; Joseph D
• Application Number:
  US10/970,718
• Publication Number:
  US 20050111565A1
• Time in Patent Office: 1,838 Days
• Field of Search: 714/774, 714/776
• US Class Current: 714/774
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/006 Trellis-coded modulation
• CPC Class Codes: H04L 1/0066 Parallel concatenated codes
• CPC Class Codes: H04L 1/007 Unequal error protection for format H04L1/0078; for codes per se H03M13/35
• CPC Class Codes: H04L 1/208 involving signal re-encoding
• CPC Class Codes: H04L 27/3416 in which the information is carried by both the individual signal points and the subset to which the individual points belong, e.g. using coset coding, lattice coding, or related schemes

Abstract

A system and method for encoding information is disclosed. In one embodiment, information is encoded using a high protection code for the least significant bit and a low protection code for the next three most significant bits. The remaining bits are uncoded. The high protection code may be a turbo code and the low protection code may be a trellis coded modulation code. In this embodiment, the collection of bits is then mapped according to a diagonally shifted QAM constellation technique.

Claims

1. A system for encoding a quantity of electronic information, the system comprising:

a high protection code encoder configured to encode a first portion of the quantity of information to produce a first coded portion of information;

a low protection code encoder configured to encode a second portion of the quantity of information to produce a second coded portion of information such that the high protection code encoder and the low protection code encoder encode the first and second portions based on a 16-state 4D Wei code concatenated with a rate 1/2 parallel concatenated turbo code, wherein the first portion comprises a least significant bit, the second portion comprises a next three significant bits, and wherein any remaining bits are uncoded; and

a modulator configured to map the first coded portion of information, the second coded portion of information, and a third portion of the quantity of information to at least one symbol.

2. The system of claim 1 wherein the high protection code encoder does not limit the asymptotic performance of the system for encoding a quantity of electronic information.

3. The system of claim 1 wherein the high protection code encoder provides a free Euclidean distance d_free,hpc and the low protection code encoder provides a free Euclidean distance d_free,lpc such that d_free,hpc>

D_N^n+pd_free,lpc, wherein D_N^n+p is a distance coefficient.

4. The system of claim 3 wherein

5. The system of claim 4 wherein the system is configured to produce a signal compromising a signal set selected from the group comprising one of:

1D lattice-type signal sets and 2D lattice-type signal sets.

6. The system of claim 3 wherein D₄¹=D₄²=√

{square root over (2)}, and D₄³=D₄⁴=2.

7. The system of claim 6 wherein the high protection encoder is configured to produce a signal comprising a 4D lattice-type signal set.

8. The system of claim 1 wherein the Wei code is consistent with ITU G.992.1 standard.

9. The system of claim 1 wherein the modulator is configured to use at least one diagonally shifted quadrature amplitude modulation constellation.

10. The system of claim 1, wherein the high protection code encoder further comprises:

two rate 1/2 binary recursive systematic convolutional (RSC) encoders; and

a random interleaver,

wherein the random interleaver separates the two rate 1/2 binary RSC encoders with a size of 1,024 bits.

11. A system for encoding a quantity of electronic information, the system comprising:

means for encoding a first portion of the quantity of information according to a high protection code to produce a first coded portion of information;

means for encoding a second portion of the quantity of information according to a low protection code to produce a second coded portion of information such that the means for encoding a first portion and the means for encoding a second portion encode the first and second portions based on a 16-state 4D Wei code concatenated with a rate 1/2 parallel concatenated turbo code, wherein the first portion comprises a least significant bit portion, the second portion comprises a next least significant bit portion, and wherein any remaining bits are uncoded; and

means for mapping the first coded portion of information, the second coded portion of information, and a third portion of the quantity of information to at least one symbol.