High performance stress-enhance MOSFET and method of manufacture
First Claim
Patent Images
1. A method of manufacturing a semiconductor structure comprising:
- forming, simultaneously, a layered structure with an underlying stress inducing material in a p-type field-effect-transistor (PFET) channel region and a n-type field-effect-transistor (NFET) channel region, wherein the layered structure with the underlying stress inducing material comprises a top layer of Si of uniform thickness and the underlying layer of SiGe;
forming on the top layer of Si of uniform thickness sidewall spacers of different sizes on NFET and PFET regions; and
etching an island in the NFET channel region and the PFET channel region comprising a channel length corresponding to the different sizes of the sidewall spacers, wherein the channel length of the NFET creates a higher resultant stress component in the NFET channel region than the PFET channel region; and
forming a stress inducing material in etched portions of the PFET channel region creating an opposite stress component in the PFET channel region than in the NFET channel region.
7 Assignments
0 Petitions
Accused Products
Abstract
A semiconductor structure and method of manufacturing and more particularly a CMOS device with a stress inducing material embedded in both gates and also in the source/drain region of the PFET. The PFET region and the NFET region having a different sized gate to vary the device performance of the NFET and the PFET.
117 Citations
10 Claims
-
1. A method of manufacturing a semiconductor structure comprising:
-
forming, simultaneously, a layered structure with an underlying stress inducing material in a p-type field-effect-transistor (PFET) channel region and a n-type field-effect-transistor (NFET) channel region, wherein the layered structure with the underlying stress inducing material comprises a top layer of Si of uniform thickness and the underlying layer of SiGe; forming on the top layer of Si of uniform thickness sidewall spacers of different sizes on NFET and PFET regions; and etching an island in the NFET channel region and the PFET channel region comprising a channel length corresponding to the different sizes of the sidewall spacers, wherein the channel length of the NFET creates a higher resultant stress component in the NFET channel region than the PFET channel region; and forming a stress inducing material in etched portions of the PFET channel region creating an opposite stress component in the PFET channel region than in the NFET channel region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
Specification