Semiconductor device and method of manufacture

• US 7,615,435 B2
• Filed: 07/31/2007
• Issued: 11/10/2009
• Est. Priority Date: 07/31/2007
• Status: Active Grant

• Current Assignee: Veeco Instruments Incorporated
• Original Assignee: International Business Machines Corporation
• Inventors: Liu, Yaocheng, Gluschenkov, Oleg, Jain, Sameer
• Primary Examiner(s): PRENTY, MARK V
• Application Number:
  US11/830,867
• Publication Number:
  US 20090032840A1
• Time in Patent Office: 833 Days
• Field of Search: 438/199, 438/154, 438/229
• US Class Current: 438/199
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7847 using a memorization technique, e.g. re-crystallization under strain, bonding on a substrate having a thermal expansion coefficient different from the one of the region
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A semiconductor device and method of manufacture and, more particularly, a semiconductor device having strain films and a method of manufacture. The device includes an embedded SiGeC layer in source and drain regions of an NFET device and an embedded SiGe layer in source and drain regions of a PFET device. The PFET device is subject to compressive strain. The method includes embedding SiGe in source and drain regions of an NFET device and implanting carbon in the embedded SiGe forming an SiGeC layer in the source and drain regions of the NFET device. The SiGeC is melt laser annealed to uniformly distribute the carbon in the SiGeC layer, thereby counteracting a strain generated by the embedded SiGe.

Claims

1. A method, comprising:

embedding SiGe in source and drain regions of an NFET device;

implanting carbon in the embedded SiGe forming an SiGeC layer in the source and drain regions of the NFET device; and

heating the SiGeC to uniformly distribute the carbon in the SiGeC layer, thereby counteracting a strain generated by the embedded SiGe, wherein;

the heating is a melt laser anneal;

the heating is below a melting point of an underlying substrate; and

the carbon is implanted before or after a rapid thermal anneal of the source and drain regions of the NFET device;

the method further comprising;

embedding SiGe in source and drain regions of a PFET device and blocking the source and drain regions of the PFET device during the implanting step; and

masking the PFET device with a same mask during the implanting step and implantation of the source and drain regions of the NFET device,

wherein the embedding SiGe in the source and drain regions of the NFET device is performed at a same time as the embedding SiGe in the source and drain regions of the PFET device.