Two mask floating gate EEPROM and method of making
First Claim
1. A method of making a floating gate transistor, comprising:
- providing a semiconductor active area;
forming a tunnel dielectric layer over the active area;
forming a floating gate layer over the tunnel dielectric layer;
forming a first photoresist mask over the floating gate layer;
patterning the floating gate layer using the first photoresist mask to form a floating gate rail;
doping the active area using the floating gate rail as a mask to form source and drain regions in the active area;
forming an intergate insulating layer adjacent to lower portions of side surfaces of the floating gate rail;
forming a control gate dielectric layer over and adjacent to upper portions of the side surfaces of the floating gate rail;
forming a control gate layer over the control gate dielectric layer;
forming a second photoresist mask over the control gate layer; and
patterning the control gate layer, the control gate dielectric layer, the floating gate rail, the tunnel dielectric layer and the active area using the second photoresist mask to form a control gate, a control gate dielectric, a floating gate, a tunnel dielectric and a channel island region.
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Abstract
There is provided a floating gate transistor, such as an EEPROM transistor, and method of making the transistor using two masking steps. The method of making a transistor includes patterning a floating gate layer using a first photoresist mask to form a floating gate rail and doping an active area using the floating gate rail as a mask to form source and drain regions in the active area. The method also includes patterning a control gate layer, a control gate dielectric layer, the floating gate rail, a tunnel dielectric layer and the active area using a second photoresist mask to form a control gate, a control gate dielectric, a floating gate, a tunnel dielectric and a channel island region.
183 Citations
42 Claims
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1. A method of making a floating gate transistor, comprising:
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providing a semiconductor active area; forming a tunnel dielectric layer over the active area; forming a floating gate layer over the tunnel dielectric layer; forming a first photoresist mask over the floating gate layer; patterning the floating gate layer using the first photoresist mask to form a floating gate rail; doping the active area using the floating gate rail as a mask to form source and drain regions in the active area; forming an intergate insulating layer adjacent to lower portions of side surfaces of the floating gate rail; forming a control gate dielectric layer over and adjacent to upper portions of the side surfaces of the floating gate rail; forming a control gate layer over the control gate dielectric layer; forming a second photoresist mask over the control gate layer; and patterning the control gate layer, the control gate dielectric layer, the floating gate rail, the tunnel dielectric layer and the active area using the second photoresist mask to form a control gate, a control gate dielectric, a floating gate, a tunnel dielectric and a channel island region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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28. A method of forming an array of floating gate transistors, comprising:
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forming at least portions of a plurality of floating gates over a tunnel dielectric located over a semiconductor active area; wherein the step of forming the at least portions of the plurality of floating gates comprises; providing the semiconductor active area; forming a tunnel dielectric layer over the active area; forming a floating gate layer over the tunnel dielectric layer; forming a first photoresist mask over the floating gate layer and patterning the floating gate layer using the first photoresist mask to form the plurality of the floating gate portions comprising floating gate rails; doping the active area using the at least portions of the plurality of floating gates as a mask to form a plurality of bit lines in the active area; wherein the step of doping the active area comprises; doping the active area using the floating gate rails as a mask to form the plurality of bit lines containing transistor source and drain regions; forming an intergate insulating layer between lower portions of side surfaces of the at least portions of the plurality of floating gates; forming a control gate dielectric on exposed upper surfaces of the at least portions of the floating gates and on exposed upper portions of side surfaces of the at least portions of the floating gates; and forming a plurality of word lines over the control dielectric and over the integrate insulating layer; wherein the steps of forming the control gate dielectric and forming the plurality of word lines comprise; forming a control gate dielectric layer and a control gate layer over and adjacent to upper portions of the side surfaces of the floating gate rails; forming a second photoresist mask over the control gate layer; and patterning the control gate layer, the control gate dielectric layer, the floating gate rails, the tunnel dielectric layer and the active area using the second photoresist mask to form the plurality of word lines containing transistor control gates, a plurality of control gate dielectrics, a plurality of floating gates, a plurality of tunnel dielectrics and a plurality of channel island regions. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35, 36, 37, 42)
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38. A method of making a floating gate transistor, comprising forming the entire floating gate transistor using two photolithographic masking steps wherein a channel island region and at least one of a control gate and a floating gate are etched using a same mask such that a semiconductor channel region of the floating gate transistor is formed in the etched channel island region, the method comprising:
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providing a semiconductor active area; forming a tunnel dielectric layer over the active area; forming a floating gate layer over the tunnel dielectric layer; forming a first photoresist mask over the floating gate layer in a first photolithographic masking step; patterning the floating gate layer using the first photoresist mask to form a floating gate rail; doping the active area using the floating gate rail as a mask to form source and drain regions in the active area; forming an intergate insulating layer adjacent to lower portions of side surfaces of the floating gate rail; forming a control gate dielectric layer over and adjacent to upper portions of the side surfaces of the floating gate rail; forming a control gate layer over the control gate dielectric layer; forming a second photoresist mask over the control gate layer in a second photolithographic masking step; and patterning the control gate layer, the control gate dielectric layer, the floating gate rail, the tunnel dielectric layer and the active area using the second photoresist mask to form the control gate, a control gate dielectric, the floating gate, a tunnel dielectric and the channel island region. - View Dependent Claims (39, 40, 41)
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Specification