Structure for implementation of back-illuminated CMOS or CCD imagers

• US 7,615,808 B2
• Filed: 09/13/2005
• Issued: 11/10/2009
• Est. Priority Date: 09/17/2004
• Status: Active Grant

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Pain, Bedabrata, Cunningham, Thomas J.
• Primary Examiner(s): Ngo; Ngan
• Assistant Examiner(s): Liu; Benjamin Tzu-Hung
• Application Number:
  US11/226,903
• Publication Number:
  US 20060076590A1
• Time in Patent Office: 1,519 Days
• Field of Search: 257/291, 257/292, 257/294, 257/444, 257/460, 257/E27.133, 257/E27.134, 257/228, 257/233, 257/447
• US Class Current: 257/228
• CPC Class Codes: H01L 27/14601 Structural or functional details thereof
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/1462 Coatings
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14625 Optical elements or arrangements associated with the device
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14685 Process for coatings or optical elements
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H01L 31/0232 Optical elements or arrangements associated with the device H01L31/0236 takes precedence; for photovoltaic cells H01L31/054; for photovoltaic modules H02S40/20

Abstract

A structure for implementation of back-illuminated CMOS or CCD imagers. An epitaxial silicon layer is connected with a passivation layer, acting as a junction anode. The epitaxial silicon layer converts light passing through the passivation layer and collected by the imaging structure to photoelectrons. A semiconductor well is also provided, located opposite the passivation layer with respect to the epitaxial silicon layer, acting as a junction cathode. Prior to detection, light does not pass through a dielectric separating interconnection metal layers.

Claims

1. A backside illuminated imaging structure comprising:

a passivation layer;

a silicon layer connected with the passivation layer, acting as a junction anode, the silicon layer adapted to convert light passing through the passivation layer and collected by the imaging structure to photoelectrons;

a semiconductor well of a first conductivity type, located opposite the passivation layer with respect to the silicon layer, acting as a junction cathode;

a transistor connected to the imaging structure, wherein a doped region of the transistor is located within the silicon layer; and

a reflector layer adapted to receive photons passing through the silicon layer and to reflect the photons back to the silicon layer.

2. The structure of claim 1, further comprising metal pads facing an illumination side of the structure.

3. The structure of claim 1, further comprising:

an anti-reflection coating and a microlens, located above the passivation layer.

4. The structure of claim 3, further comprising a color filter.

5. The structure of claim 4, wherein the passivation layer is directly connected with the silicon layer, the anti-reflection coating is directly connected with the passivation layer, and the color filter is directly connected with the anti-reflection coating.

6. The structure of claim 1, wherein the silicon layer comprises an implanted region of a second conductivity type different from the first conductivity type.

7. The structure of claim 1, further comprising a substrate.

8. The structure of claim 7, wherein the substrate is a glass or organic substrate.

9. The structure of claim 1, further comprising interconnection metal layers.

10. The structure of claim 9, wherein the interconnection metal layers are separated by dielectric.

11. The structure of claim 10, wherein the reflector layer is embedded in the dielectric.

12. The structure of claim 1, wherein the reflector layer is a metal layer.

13. A CMOS imager comprising the structure of claim 1.

14. A CCD imager comprising the structure of claim 1.

15. A backside illuminated imaging structure, comprising:

a base layer;

a silicon device layer connected with the base layer, wherein light is absorbed in the silicon device layer, through a surface of the silicon device layer not connected with the base layer, without passing through the base layer;

a transistor connected to the photodiode array, wherein the transistor is located in its entirety within at least one of the silicon layer and the inter-layer dielectric; and

metal pads, residing on an illumination side of the structure and connected with the surface of the silicon device layer not connected with the base layer.

16. The structure of claim 15, further comprising a reflector layer adapted to receive photons passing through the silicon device layer and to reflect the photons back to the silicon device layer.

17. A wafer comprising:

a passivation layer;

a silicon layer connected with the passivation layer, the silicon layer comprising a photodiode array, adapted to convert light passing through the passivation layer;

inter-layer dielectric connected with the silicon layer;

a transistor connected to the photodiode array, wherein the transistor is located in its entirety within at least one of the silicon layer and the inter-layer dielectric;

a base connected with the inter-layer dielectric; and

a plurality of metal pads connected with the passivation layer.

18. The wafer of claim 17, further comprising a plurality of metal reflectors located in the inter-layer dielectric.

19. The wafer of claim 17, further comprising an anti-reflection layer located above the passivation layer.

20. The wafer of claim 17, further comprising a microlens array located above the passivation layer.

21. The wafer of claim 20, further comprising a color filter array, located under the microlens array.

22. The wafer of claim 17, further comprising a plurality of MOS gates located in the inter-layer dielectric and connected with the photodiode array.

23. A light detection method comprising:

providing a junction comprising a junction cathode and a silicon layer acting as a junction anode;

connecting a passivation layer to the silicon layer on a side of the silicon layer opposite the junction cathode;

inputting light to the silicon layer through the passivation layer, whereby light is detected in the silicon layer; and

providing a reflector to receive photons passing through the silicon layer and to reflect the photons back to the silicon layer; and

providing non-imaging support electronics in the silicon layer.

24. The method of claim 23, wherein the silicon layer is an epitaxial silicon layer.

25. The method of claim 23, wherein the junction is part of a CMOS imager.

26. The method of claim 23, wherein the junction is part of a CCD imager.

27. The method of claim 24, further comprising:

providing interconnection metal layers separated by dielectric, wherein, prior to detection, light does not pass through the dielectric.

28. An illumination method comprising:

providing a base layer;

providing a silicon device layer having a first surface not connected with the base layer and a second surface connected with the base layer;

connecting metal pads on a same side of the silicon device layer as the first surface of the silicon device layer with the first surface of the silicon device layer;

impinging light through the first surface of the silicon device layer;

providing non-imaging support electronics in the silicon device layer; and

absorbing light in the silicon device layer.