Diffused drain transistor

• US 7,615,822 B1
• Filed: 12/23/2002
• Issued: 11/10/2009
• Est. Priority Date: 12/23/2002
• Status: Expired due to Term

• Current Assignee: Volterra Semiconductor Corporation (Analog Devices, Inc.)
• Original Assignee: Volterra Semiconductor Corporation (Analog Devices, Inc.)
• Inventors: Zuniga, Marco A.
• Primary Examiner(s): Wilson; Allan R.
• Application Number:
  US10/327,794
• Time in Patent Office: 2,514 Days
• Field of Search: 257/288, 257/327, 257335-338, 257/340, 257342-351, 257/408, 257/E21.435, 257/E21.437, 257/E29.266, 257/E29.268, 257/E29.278
• US Class Current: 257/336
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A transistor has a source that includes a first impurity region with a first volume and a first surface area on a surface of the transistor. The transistor also has a drain that includes a second impurity region with a second volume and a second surface area on a surface of the transistor, a third impurity region with a third volume that overlaps and extends deeper than the second volume of the second impurity region, and a fourth impurity region with a fourth volume and a third surface area. The third surface area is located in the second surface area of the second impurity region. Additionally, the second and third impurity regions have a lower concentration of impurities than the fourth impurity region. The transistor also has a gate to control a depletion region between the source and the drain.

Claims

1. A transistor comprising:

a drain including;

a first impurity region of a first conductivity type having a first volume and a first surface area on a surface of the transistor,

a second impurity region of the first conductivity type with a lower concentration of impurities than the first impurity region, the second impurity region having a second volume and a second surface area on the surface of the transistor, wherein the second volume surrounds and abuts the first volume and extends below the first volume, and the second surface area is adjacent to the first surface area,

a third impurity region of the first conductivity type with a lower concentration of impurities than the second impurity region, the third impurity region having a third volume and a third surface area on the surface of the transistor, wherein the third volume surrounds and abuts the second volume, and has a lower boundary that is vertically aligned with a lower boundary of the second volume, and wherein the third surface area is adjacent to the second surface area, and

a fourth impurity region of the first conductivity type with a lower concentration of impurities than the second impurity region, the fourth impurity region having a fourth volume, wherein the fourth volume extends below the second volume and has an upper boundary that abuts the lower boundary of the second volume and an outer boundary that is laterally aligned with an outer boundary of the second volume;

a source including a fifth impurity region with a fifth volume and a fifth surface area on the surface of the transistor; and

a gate to control a depletion region between the source and the drain,

wherein the fourth impurity region has a lower concentration of impurities than the third impurity region.

2. The transistor of claim 1, wherein the third impurity region is not self-aligned with respect to the gate.

3. The transistor of claim 1, wherein the third impurity region is self-aligned with respect to the gate.

4. The transistor of claim 1, wherein the second surface area surrounds the first surface area.

5. The transistor of claim 1, wherein the third surface area surrounds the second surface area.

6. The transistor of claim 1, wherein the third surface area of the third impurity region abuts a gate oxide layer corresponding to the gate.

7. The transistor of claim 1, wherein the fourth impurity region is positioned and has a concentration sufficient to reduce resistive and capacitive power loss.

8. The transistor of claim 1, wherein the fourth impurity region is positioned and has a concentration sufficient to increase the maximum power density the transistor can sustain.

9. The transistor of claim 1, wherein the fourth impurity region is positioned and has a concentration sufficient to improve hot electron behavior and not affect the junction breakdown of the transistor.

10. The transistor of claim 1, wherein the second impurity region and the fourth impurity region are formed by one or more CMOS processing techniques.

11. A semiconductor device, comprising:

a semiconductor layer of a first conductivity type;

an impurity well of a second conductivity type formed in a surface area of the semiconductor layer;

a first distributed device having a drain and a source formed in a surface in the impurity well and a gate to control a depletion region between the source and the drain; and

a second distributed device formed outside the surface area of the impurity well including;

a drain including;

a first impurity region of a second conductivity type having a first volume and a first surface area on a surface of the transistor,

a second impurity region of the second conductivity type with a lower concentration of impurities than the first impurity region, the second impurity region having a second volume and a second surface area on the surface of the transistor, wherein the second volume surrounds and abuts the first volume and extends below the first volume, and the second surface area is adjacent to the first surface area,

a third impurity region of the second conductivity type with a lower concentration of impurities than the second impurity region, the third impurity region having a third volume and a third surface area on the surface of the transistor, wherein the third volume surrounds and abuts the second volume, and has a lower boundary that is vertically aligned with a lower boundary of the second volume, and wherein the third surface area is adjacent to the second surface area, and

a fourth impurity region of the second (conductivity type with a lower concentration of impurities than the second impurity region, the fourth impurity region having a fourth volume, wherein the fourth volume extends below the second volume and has an upper boundary that abuts the lower boundary of the second volume and an outer boundary that is laterally aligned with an outer boundary of the second volume;

a source including a fifth impurity region with a fifth volume and a fifth surface area on the surface of the transistor;

a gate to control a depletion region between the source and the drain;

wherein the drain of the first distributed device and the drain of the second distributed device each includes a plurality of drains,

wherein the source of the first distributed device and the source of the second distributed device each includes a plurality of sources,

wherein the gate of the first distributed device and the gate of the second distributed device each includes a plurality of gates, and

wherein the fourth impurity region has a lower concentration of impurities than the third impurity region.

12. The semiconductor device of claim 11, wherein the plurality of drains and sources are arranged in a square fet implementation.

13. The semiconductor device of claim 11, wherein the plurality of drains and sources are arranged in a fingered array implementation.

14. The semiconductor device of claim 11, wherein the third impurity region is not self-aligned with respect to the gate.

15. The semiconductor device of claim 11, wherein the third impurity region is self-aligned with respect to the gate.

16. The semiconductor device of claim 11, wherein the second surface area surrounds the first surface area.

17. The semiconductor device of claim 11, wherein the third surface area surrounds the second surface area.

18. The semiconductor device of claim 11, wherein the third surface area of the third impurity region abuts a gate oxide layer corresponding to the gate.