Semiconductor device

• US 7,615,846 B2
• Filed: 12/31/2007
• Issued: 11/10/2009
• Est. Priority Date: 07/17/2007
• Status: Active Grant

• Current Assignee: Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: Harada, Tatsuo
• Primary Examiner(s): Louie; Wai-Sing
• Assistant Examiner(s): Jahan; Bilkis
• Application Number:
  US11/967,718
• Publication Number:
  US 20090020852A1
• Time in Patent Office: 680 Days
• Field of Search: 257/578, 257/579, 257/E29.027, 257/E29.066, 257/E29.197, 257/E29.201, 257/E21.382
• US Class Current: 257/579
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

An emitter layer is provided in stripes in a direction orthogonal to an effective gate trench region connected to a gate electrode and a dummy trench region isolated from the gate electrode. A width of the emitter layer is determined to satisfy a predetermined relational expression so as not to cause latch-up in an underlying P base layer. In the predetermined relational expression, an upper limit value of the width W of the emitter layer is (3500/Rspb)·Wso·exp(decimation ratio), where Rspb is a sheet resistance of the P base layer immediately below the emitter layer, Wso is an interval between the trenches, and the decimation ratio is a ratio of the number of the effective gate trench region to the total number of the trench regions. Variations in saturation current in a trench IGBT can be suppressed, and a tolerance of an Reverse Bias Safe Operation Area can be improved.

Claims

1. A semiconductor device, comprising:

a first semiconductor layer;

a second semiconductor layer formed above said first semiconductor layer;

a plurality of trench regions, each formed extending from said second semiconductor layer to said first semiconductor layer, formed being spaced from each other, the trench regions including an effective gate trench region having a gate electrode layer formed on an inner wall thereof with a gate insulating film interposed in between and electrically connected to a gate electrode, and a dummy trench region isolated from said gate electrode; and

third semiconductor layers formed, on a surface of said second semiconductor layer, orthogonally to the plurality of trench regions and being spaced from each other, and electrically connected to a first electrode layer, the third semiconductor layer having a width W along a direction in which the trench regions extend, in a portion contacting said first electrode layer, satisfying the relation of;

W≦

(K/Rspb)·

Wso·

F(m),

where K is a constant, Rspb is a sheet resistance of the second semiconductor layer, Wso is a pitch of said trench regions, F( ) is a predetermined function, and m is a decimation ratio representing a ratio of a number of the effective gate trench region to a total number of said plurality of trench regions.

2. The semiconductor device according to claim 1, wherein said K is 3500, and said F(m) is represented by exp (m) that is an exponential function of a base, e, of natural logarithms.

3. The semiconductor device according to claim 1, wherein said W has a magnitude not less than a depth of the third semiconductor layer to said second semiconductor layer.

4. The semiconductor device according to claim 1, wherein an interval of adjacent said third semiconductor layers is not less than a sum of said W and double a depth of the third semiconductor layer to the second semiconductor layer.

5. The semiconductor device according to claim 1, wherein said third semiconductor layers each have a shape of a stripe linearly formed substantially with said width W.