Method and device for determining an operational lifetime of an integrated circuit device

• US 7,616,021 B2
• Filed: 01/18/2007
• Issued: 11/10/2009
• Est. Priority Date: 01/18/2007
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Su, Michael Zhouying, Ramirez, Amado, Papageorgiou, Vassilios
• Primary Examiner(s): Nguyen; Ha Tran T
• Assistant Examiner(s): Campbell; Shaun
• Application Number:
  US11/624,258
• Publication Number:
  US 20080174329A1
• Time in Patent Office: 1,027 Days
• Field of Search: 324/765
• US Class Current: 324/762.01
• CPC Class Codes: G01R 31/287 Procedures; Software aspects
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT

Abstract

An integrated circuit device includes a degradable test structure, a first external interface pin and a second external interface pin, a first conductive path coupling a first node of the degradable test structure and the first external interface pin, and a second conductive path coupling a second node of the degradable test structure and the second external interface pin. Another integrated circuit device includes a non-volatile memory device, a counter comprising an input configured to receive a first clock signal and an output to provide a count value, and control logic configured to store the count value of the counter in the non-volatile memory, whereby the non-volatile memory is externally accessible.

Claims

1. A method comprising:

determining a power mode of an operation of an activated integrated circuit device;

applying a test electrical bias to a degradable test structure of the integrated circuit device via an external interface pin of the integrated circuit device, wherein a magnitude of the test electrical bias is based on the power mode for the operation of the integrated circuit;

determining a degradable characteristic of the degradable test structure in response to the application of the test electrical bias to the degradable test structure; and

determining an estimated cumulative duration for which the integrated circuit device has been in operation based on the degradable characteristic.

2. An integrated circuit device comprising:

a degradable test structure;

a resistance structure having an adjustable resistance;

a first external interface pin and a second external interface pin;

a first conductive path coupling a first node of the degradable test structure and the first external interface pin via the resistance structure;

a second conductive path coupling a second node of the degradable test structure and the second external interface pin; and

control logic configured to adjust the adjustable resistance of the resistance structure based on a power mode of an operation of the integrated circuit device.

3. A system comprising:

an integrated circuit device comprising;

a non-volatile memory device;

a counter comprising an input configured to receive a first clock signal and an output to provide a count value;

a frequency divider having an input to receive a second clock signal and an output coupled to the input of the counter to provide the first clock signal;

mode control logic configured to control a frequency division ratio of the frequency divider based on a power mode of an operation of the integrated circuit device;

control logic configured to store the count value of the counter in the non-volatile memory; and

means for accessing the count value from the non-volatile memory external from the integrated circuit device.