Charge pump for PLL/DLL

• US 7,616,035 B2
• Filed: 06/16/2008
• Issued: 11/10/2009
• Est. Priority Date: 12/11/2003
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Haerle, Dieter
• Primary Examiner(s): Donovan; Lincoln
• Assistant Examiner(s): Hernandez; William
• Application Number:
  US12/214,053
• Publication Number:
  US 20080252342A1
• Time in Patent Office: 512 Days
• Field of Search: 327147-149, 327156-158, 327/161, 331/17, 331/25, 375373-376
• US Class Current: 327/157
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/0895 Details of the current generators H03L7/0893 takes precedence

Abstract

A charge pump for use in a locked loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage. The charge pump further includes a startup circuit to establish a predetermined voltage level at the charge pump output node during startup.

Claims

1. A locked loop comprising:

a phase detector for providing an up output signal and a down output signal;

a charge pump comprising;

pull-up circuitry that comprises a current source and a controlled transistor having a gate adapted for connection to the up output signal for being controlled thereby, the pull-up circuitry connected between a positive voltage supply and an output node of the charge pump;

pull-down circuitry that comprises a current source and a controlled transistor having a gate adapted for connection to the down output signal for being controlled thereby, the pull-down circuitry connected between a ground voltage supply and the charge pump output node;

a reference current source for controlling the current in the current sources of the pull-up and pull-down circuitries;

an operational amplifier having two inputs and an output, and the operational amplifier configured to reduce phase error, one of the inputs of the operational amplifier connected to the charge pump output node; and

a startup circuit to establish a predetermined voltage level at the charge pump output node during startup; and

a capacitor connected to the charge pump output node.

2. The locked loop as claimed in claim 1 wherein the current sources in each of the pull-up circuitry and the pull-down circuitry comprises a transistor connected in series with the respective controlled transistor.

3. The locked loop as claimed in claim 2 wherein the controlled transistor in the pull-up circuitry is connected to the positive voltage supply, and the current source transistor in the pull-up circuitry is connected to the charge pump output node.

4. The locked loop as claimed in claim 2 wherein the controlled transistor in the pull-down circuitry is connected to the ground voltage supply, and the current source transistor in the pull-down circuitry is connected to the charge pump output node.

5. The locked loop as claimed in claim 1 further comprising additional pull-up circuitry and additional pull-down circuitry connected together at an additional node.

6. The locked loop as claimed in claim 5 wherein the additional pull-up circuitry and the pull-up circuitry have corresponding transistors with source and drain terminals connected in the same manner, and the additional pull-down circuitry and the pull-down circuitry have corresponding transistors with source and drain terminals connected in the same manner.

7. The locked loop as claimed in claim 6 wherein a gate of a controlled transistor in the additional pull-up circuitry is connected to a first voltage supply, and a gate of a controlled transistor in the additional pull-down circuitry is connected to a second voltage supply.

8. The locked loop as claimed in claim 6 wherein the additional pull-up circuitry and the pull-up circuitry have correspondingly same sized transistors, and the additional pull-down circuitry and the pull-down circuitry have correspondingly same sized transistors.

9. The locked loop as claimed in claim 5 wherein the other input of the operational amplifier is connected to the additional node.

10. The locked loop as claimed in claim 9 wherein the output of the operational amplifier is connected to a selected one of the current source of the pull-down circuitry and the current source of the pull-up circuitry, and the reference current source is connected to the current source of the other circuitry.

11. The locked loop as claimed in claim 1 wherein the operational amplifier has an output range substantially from rail to rail.

12. The locked loop as claimed in claim 1 wherein the operational amplifier comprises two differential input stages.

13. The locked loop as claimed in claim 12 wherein the differential input stages comprise one PMOS input differential stage and one NMOS input differential stage.

14. The locked loop as claimed in claim 1 wherein the startup circuit comprises a MOS device having a source connected to a voltage supply and a gate connected to a startup control signal.

15. The locked loop as claimed in claim 14 wherein the MOS device is an NMOS device.

16. The locked loop as claimed in claim 14 wherein the voltage supply is the ground voltage supply.

17. The locked loop as claimed in claim 14 wherein the startup circuit further comprises a source follower transistor that is connected in series with the MOS device.

18. The locked loop as claimed in claim 17 wherein the voltage supply is the ground voltage supply and the source follower transistor is connected to the charge pump output node.

19. The locked loop as claimed in claim 1 further comprising a voltage controlled oscillator connected to the charge pump output node in a phase locked loop configuration.

20. The locked loop as claimed in claim 1 further comprising a voltage controlled delay line connected to the charge pump output node in a delay locked loop configuration.

21. A locked loop comprising:

a phase detector for providing an up output signal and a down output signal;

a charge pump comprising;

pull-up circuitry that comprises a current source and a controlled transistor having a gate adapted for connection to the up output signal for being controlled thereby, the pull-up circuitry connected between a positive voltage supply and an output node of the charge pump;

pull-down circuitry that comprises a current source and a controlled transistor having a gate adapted for connection to the down output signal for being controlled thereby, the pull-down circuitry connected between a ground voltage supply and the charge pump output node;

a reference current source; and

a plurality of programmable transistors, both the reference current source and the plurality of programmable transistors each configured to control the current in at least one of the current sources of the pull-up and pull-down circuitries;

a capacitor connected to the charge pump output node; and

a startup circuit connected to the charge pump output node, and the startup circuit comprising a MOS device having a source connected to a voltage supply and a gate connected to a startup control signal.

22. The locked loop as claimed in claim 21 wherein the voltage supply is the ground voltage supply.

23. The locked loop as claimed in claim 21 wherein the startup circuit further comprises a source follower transistor that is connected in series with the MOS device.

24. The locked loop as claimed in claim 23 wherein the voltage supply is the ground voltage supply and the source follower transistor is connected to the charge pump output node.