Nested transimpedance amplifier

• US 7,616,057 B2
• Filed: 12/21/2006
• Issued: 11/10/2009
• Est. Priority Date: 03/13/2001
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Sutardja, Sehat
• Primary Examiner(s): Nguyen; Patricia
• Application Number:
  US11/643,089
• Publication Number:
  US 20070103231A1
• Time in Patent Office: 1,055 Days
• Field of Search: 330/98, 330/99, 330/107, 330/100, 250/214.A
• US Class Current: 330/98
• CPC Class Codes: H03F 1/08 Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements wide-band amplifiers with inter-stage coupling networks incorporating these impedances H03F1/42
• CPC Class Codes: H03F 1/34 Negative-feedback-circuit arrangements with or without positive feedback H03F1/02 - H03F1/30, H03F1/38 - H03F1/50, H03F3/50 take precedence ; for rejection of common mode signals H03F3/45479
• CPC Class Codes: H03F 2200/331 Sigma delta modulation being used in an amplifying circuit
• CPC Class Codes: H03F 2200/36 the amplifier comprising means for increasing the bandwidth
• CPC Class Codes: H03F 2203/45528 the FBC comprising one or more passive resistors and being coupled between the LC and the IC
• CPC Class Codes: H03F 2203/45531 the FBC comprising a parallel resonance circuit and being coupled between the LC and the IC
• CPC Class Codes: H03F 2203/45652 the LC comprising one or more further dif amp stages, either identical to the dif amp or not, in cascade
• CPC Class Codes: H03F 3/08 controlled by light
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03F 3/45928 using IC blocks as the active amplifying circuit

Abstract

A differential transimpedance amplifier circuit comprises a first operational amplifier having a first inverting input, a first non-inverting input, a first inverting output and a first non-inverting output. A second operational amplifier has a second inverting input, a second non-inverting input, a second inverting output and a second non-inverting output. The second inverting output communicates with the first non-inverting input and the second non-inverting output communicates with the first inverting input. A first feedback element communicates with the first non-inverting input and the first inverting output. A second feedback element communicates with the first inverting input and the first non-inverting output. A third feedback element communicates with the second inverting input and the first inverting output. A fourth feedback element communicates with the first non-inverting input and the first non-inverting output.

Claims

1. A differential transimpedance amplifier circuit comprising:

a first operational amplifier having a first inverting input, a first non-inverting input, a first inverting output and a first non-inverting output;

a second operational amplifier having a second inverting input, a second non-inverting input, a second inverting output and a second non-inverting output, wherein the second inverting output communicates directly with the first non-inverting input and the second non-inverting output communicates directly with the first inverting input;

a first feedback element that communicates with the first non-inverting input and the first inverting output;

a second feedback element that communicates with the first inverting input and the first non-inverting output;

a third feedback element that communicates with the second inverting input and the first inverting output; and

a fourth feedback element that communicates with the second non-inverting input and the first non-inverting output.

2. The differential transimpedance amplifier circuit of claim 1 wherein the third and fourth feedback elements comprise first and second resistances, respectively.

3. The differential transimpedance amplifier circuit of claim 1 wherein the third and fourth feedback elements comprise first and second capacitances, respectively.

4. The differential transimpedance amplifier circuit of claim 1 wherein the first and second feedback elements comprise first and second resistances, respectively.

5. The differential transimpedance amplifier circuit of claim 1 wherein the first and second feedback elements comprise first and second capacitances, respectively.

8. The differential transimpedance amplifier circuit of claim 1 wherein the first and second feedback elements each comprise a resistance in parallel with a capacitance.

10. The differential transimpedance amplifier circuit of claim 1 wherein the first and second feedback elements each comprise a first resistance in series with an inductance and that are in parallel with a capacitance and a second resistance.

11. The differential transimpedance amplifier circuit of claim 10 wherein the capacitance includes a variable capacitance.

12. The differential transimpedance amplifier circuit of claim 1 wherein the first and second operational amplifiers are transconductance amplifiers.

13. A single-nested transimpedance amplifier circuit comprising:

a third operational amplifier having a third inverting input, a third non-inverting input, a third inverting output and a third non-inverting output; and

the differential transimpedance amplifier circuit of claim 1;

wherein the second inverting input communicates with the third non-inverting output and the second non-inverting input communicates with the third inverting output.

17. The single-nested differential transimpedance amplifier circuit of claim 13 further comprising:

a fifth feedback element that communicates with the third non-inverting input and the first inverting output; and

a sixth feedback element that communicates with the third inverting input and the first non-inverting output.

18. The single-nested differential transimpedance amplifier circuit of claim 17 wherein the fifth and sixth feedback elements comprise first and second capacitances.

19. A Sigma-Delta analog to digital converter comprising the differential transimpedance amplifier of claim 1.

20. The Sigma-Delta analog to digital converter of claim 19 further comprising:

a difference amplifier module that includes one input that receives an input signal;

an integrator module that communicates with an output of the difference amplifier module;

a comparator module that receives an output of the integrator module; and

a digital to analog converter module that communicates with an output of the comparator module and another input of the difference amplifier module.

21. The Sigma-Delta analog to digital converter of claim 20 further comprising a filter and decimation module that receives an output of the comparator module.

22. The Sigma-Delta analog to digital converter of claim 20 wherein at least one of the difference amplifier module, the integrator module and the comparator module includes the differential transimpedance amplifier.

45. An integrator comprising the differential transimpedance amplifier of claim 3.

6. A differential transimpedance amplifier circuit comprising:

a first operational amplifier having a first inverting input, a first non-inverting input, a first inverting output and a first non-inverting output;

a second operational amplifier having a second inverting input, a second non-inverting input, a second inverting output and a second non-inverting output, wherein the second inverting output communicates with the first non-inverting input and the second non-inverting output communicates with the first inverting input;

a first feedback element that communicates with the first non-inverting input and the first inverting output;

a second feedback element that communicates with the first inverting input and the first non-inverting output;

a third feedback element that communicates with the second inverting input and the first inverting output; and

a fourth feedback element that communicates with the second non-inverting input and the first non-inverting output,

wherein the first and second feedback elements each comprise a first resistance in series with an inductance and a second resistance that are in parallel with a capacitance.

7. The differential transimpedance amplifier circuit of claim 6 wherein the capacitance includes a variable capacitance.

9. A differential transimpedance amplifier circuit comprising:

a first operational amplifier having a first inverting input, a first non-inverting input, a first inverting output and a first non-inverting output;

a second operational amplifier having a second inverting input, a second non- inverting input, a second inverting output and a second non-inverting output, wherein the second inverting output communicates with the first non-inverting input and the second non-inverting output communicates with the first inverting input;

a first feedback element that communicates with the first non-inverting input and the first inverting output;

a second feedback element that communicates with the first inverting input and the first non-inverting output;

a third feedback element that communicates with the second inverting input and the first inverting output; and

a fourth feedback element that communicates with the second non-inverting input and the first non-inverting output,

wherein the first and second feedback elements each comprise a resistance in communication with a capacitance, and

wherein the capacitance includes a variable capacitance.

14. A double-nested differential transimpedance amplifier circuit comprising:

a single-nested transimpedance amplifier circuit comprising;

a third operational amplifier having a third inverting input, a third non-inverting input, a third inverting output and a third non-inverting output; and

a differential transimpedance amplifier circuit comprising;

a first operational amplifier having a first inverting input, a first non- inverting input, a first inverting output and a first non-inverting output;

a second operational amplifier having a second inverting input, a second non-inverting input, a second inverting output and a second non-inverting output, wherein the second inverting output communicates with the first non-inverting input and the second non-inverting output communicates with the first inverting input;

a first feedback element that communicates with the first non- inverting input and the first inverting output;

a second feedback element that communicates with the first inverting input and the first non-inverting output;

a third feedback element that communicates with the second inverting input and the first inverting output; and

a fourth feedback element that communicates with the second non- inverting input and the first non-inverting output; and

a fourth operational amplifier having a fourth inverting input, a fourth non- inverting input, a fourth inverting output and a fourth non-inverting output,

wherein the second inverting input communicates with the third non-inverting output and the second non-inverting input communicates with the third inverting output, and

wherein the fourth inverting output communicates with the third non-inverting output and the fourth non-inverting output communicates with the third inverting input.

15. The double-nested differential transimpedance amplifier of claim 14 further comprising:

a fifth feedback element that communicates with the fourth inverting output and the first inverting output; and

a sixth feedback element that communicates with the fourth non-inverting output and the first non-inverting output.

16. The double-nested differential transimpedance amplifier circuit of claim 15 wherein the fifth and sixth feedback elements comprise first and second resistances, respectively.

23. A differential transimpedance amplifier circuit comprising:

first amplifying means for amplifying having a first inverting input, a first non-inverting input, a first inverting output and a first non-inverting output;

second amplifying means for amplifying having a second inverting input, a second non-inverting input, a second inverting output and a second non-inverting output, wherein the second inverting output communicates directly with the first non-inverting input and the second non-inverting output communicates directly with the first inverting input;

first feedback means for providing feedback that communicates with the first non-inverting input and the first inverting output;

second feedback means for providing feedback that communicates with the first inverting input and the first non-inverting output;

third feedback means for providing feedback that communicates with the second inverting input and the first inverting output; and

fourth feedback means for providing feedback that communicates with the second non-inverting input and the first non-inverting output.

24. The differential transimpedance amplifier circuit of claim 23 wherein the third and fourth feedback means comprise first and second resistance means for providing resistance, respectively.

25. The differential transimpedance amplifier circuit of claim 23 wherein the third and fourth feedback means comprise first and second capacitances for providing capacitance, respectively.

26. The differential transimpedance amplifier circuit of claim 23 wherein the first and second feedback means comprise first and second resistance means for providing resistance, respectively.

27. The differential transimpedance amplifier circuit of claim 23 wherein the first and second feedback means comprise first and second capacitance means for providing capacitance, respectively.

30. The differential transimpedance amplifier circuit of claim 23 wherein the first and second feedback means each comprise resistance means for providing resistance in parallel with capacitance means for providing capacitance.

32. The differential transimpedance amplifier circuit of claim 23 wherein the first and second feedback means each comprise first resistance means for providing resistance in series with inductance means for providing inductance and that are in parallel with capacitance means for providing capacitance and second resistance means for providing resistance.

33. The differential transimpedance amplifier circuit of claim 32 wherein the capacitance means provides a variable capacitance.

34. The differential transimpedance amplifier circuit of claim 23 wherein the first and second amplifying means include transconductance amplifiers.

35. A single-nested transimpedance amplifier circuit comprising:

third amplifying means for amplifying having a third inverting input, a third non-inverting input, a third inverting output and a third non-inverting output; and

the differential transimpedance amplifier circuit of claim 23;

wherein the second inverting input communicates with the third non-inverting output and the second non-inverting input communicates with the third inverting output.

39. The single-nested differential transimpedance amplifier circuit of claim 35 further comprising:

fifth feedback means for providing feedback that communicates with the third non-inverting input and the first inverting output; and

sixth feedback means for providing feedback that communicates with the third inverting input and the first non-inverting output.

40. The single-nested differential transimpedance amplifier circuit of claim 39 wherein the fifth and sixth feedback means comprise first and second capacitance means for providing capacitance.

41. A Sigma-Delta analog to digital converter comprising the differential transimpedance amplifier of claim 23.

42. The Sigma-Delta analog to digital converter of claim 41 further comprising:

difference amplifier means for amplifying that includes one input that receives an input signal;

integrator means for integrating that communicates with an output of the difference amplifier means;

comparator means for comparing that receives an output of the integrator means; and

digital to analog converter means for converting that communicates with an output of the comparator means and another input of the difference amplifier means.

43. The Sigma-Delta analog to digital converter of claim 42 further comprising filter and decimation means for filtering and decimating and that receives an output of the comparator means.

44. The Sigma-Delta analog to digital converter of claim 42 wherein at least one of the difference amplifier means, the integrator means and the comparator means includes the differential transimpedance amplifier.

46. An integrator comprising the differential transimpedance amplifier of claim 25.

28. A differential transimpedance amplifier circuit comprising:

first amplifying means for amplifying having a first inverting input, a first non- inverting input, a first inverting output and a first non-inverting output;

second amplifying means for amplifying having a second inverting input, a second non-inverting input, a second inverting output and a second non-inverting output. wherein the second inverting output communicates with the first non-inverting input and the second non-inverting output communicates with the first inverting input;

first feedback means for providing feedback that communicates with the first non- inverting input and the first inverting output;

second feedback means for providing feedback that communicates with the first inverting input and the first non-inverting output;

third feedback means for providing feedback that communicates with the second inverting input and the first inverting output; and

fourth feedback means for providing feedback that communicates with the second non-inverting input and the first non-inverting output,

wherein the first and second feedback means each comprise first resistance means for providing resistance in series with inductance means for providing inductance and second resistance means for providing resistance that are in parallel with a capacitance means for providing capacitance.

29. The differential transimpedance amplifier circuit of claim 28 wherein the capacitance means provides a variable capacitance.

31. A differential transimpedance amplifier circuit comprising:

first amplifying means for amplifying having a first inverting input, a first non- inverting input, a first inverting output and a first non-inverting output;

second amplifying means for amplifying having a second inverting input, a second non-inverting input, a second inverting output and a second non-inverting output, wherein the second inverting output communicates with the first non-inverting input and the second non-inverting output communicates with the first inverting input;

first feedback means for providing feedback that communicates with the first non- inverting input and the first inverting output;

second feedback means for providing feedback that communicates with the first inverting input and the first non-inverting output;

third feedback means for providing feedback that communicates with the second inverting input and the first inverting output; and

fourth feedback means for providing feedback that communicates with the second non-inverting input and the first non-inverting output,

wherein the first and second feedback means each comprise resistance means for communicating with capacitance means for providing capacitance, and wherein the capacitance means provides a variable capacitance.

36. A double-nested differential transimpedance amplifier circuit comprising:

a single-nested transimpedance amplifier circuit comprising;

third amplifying means for amplifying having a third inverting input, a third non-inverting input, a third inverting output and a third non-inverting output; and

a differential transimpedance amplifier circuit comprising;

first amplifying means for amplifying having a first inverting input, a first non-inverting input, a first inverting output and a first non-inverting output;

second amplifying means for amplifying having a second inverting input, a second non-inverting input, a second inverting output and a second non- inverting output, wherein the second inverting output communicates with the first non- inverting input and the second non-inverting output communicates with the first inverting input;

first feedback means for providing feedback that communicates with the first non-inverting input and the first inverting output;

second feedback means for providing feedback that communicates with the first inverting input and the first non-inverting output;

third feedback means for providing feedback that communicates with the second inverting input and the first inverting output; and

fourth feedback means for providing feedback that communicates with the second non-inverting input and the first non-inverting output; and

fourth amplifying means for amplifying having a fourth inverting input, a fourth non-inverting input, a fourth inverting output and a fourth non-inverting output,

wherein the second inverting input communicates with the third non-inverting output and the second non-inverting input communicates with the third inverting output, and

wherein the fourth inverting output communicates with the third non-inverting output and the fourth non-inverting output communicates with the third inverting input.

37. The double-nested differential transimpedance amplifier of claim 36 further comprising:

fifth feedback means for providing feedback that communicates with the fourth inverting output and the first inverting output; and

sixth feedback means for providing feedback that communicates with the fourth non-inverting output and the first non-inverting output.

38. The double-nested differential transimpedance amplifier circuit of claim 37 wherein the fifth and sixth feedback means comprise first and second resistance means for providing resistance, respectively.

47. A circuit comprising:

a transimpedance amplifier comprising;

a first operational amplifier having a first inverting input, a first non- inverting input, a first inverting output and a first non-inverting output;

a second operational amplifier having a second inverting input, a second non-inverting input, a second inverting output and a second non-inverting output,

wherein the second inverting output communicates directly with the first non-inverting input and the second non-inverting output communicates directly with the first inverting input;

a first feedback element that communicates with the first non-inverting input and the first inverting output;

a second feedback element that communicates with the first inverting input and the first non-inverting output;

a third feedback element that communicates with the second inverting input and the first inverting output; and

a fourth feedback element that communicates with the second non- inverting input and the first non-inverting output.

48. The circuit of claim 47 wherein said first operational amplifier, said first feedback element, and said second feedback element perform as a transimpedance stage.

49. The circuit of claim 47 wherein said first inverting input and said a first non-inverting input include a current signal, and

wherein said first inverting output and said first non-inverting output include a voltage signal that is a converted amplification of said current signal.

50. A transimpedance amplifier comprising:

a first operational amplifier having a first inverting input, a first non-inverting input, a first inverting output and a first non-inverting output;

a second operational amplifier having a second inverting input, a second non- inverting input, a second inverting output and a second non-inverting output, wherein the second inverting output communicates with the first non-inverting input and the second non-inverting output communicates with the first inverting input;

a first feedback element that communicates with the first non-inverting input and the first inverting output;

a second feedback element that communicates with the first inverting input and the first non-inverting output;

a third feedback element that communicates with the second inverting input and the first inverting output; and

a fourth feedback element that communicates with the second non-inverting input and the first non-inverting output,

wherein input of said second operational amplifier is an input of the transimpedance amplifier.

51. The transimpedance amplifier of claim 50 wherein said output of said second operational amplifier is a current signal that is provided to said first operational amplifier.

52. A transimpedance amplifier comprising:

a first operational amplifier having a first inverting input, a first non-inverting input, a first inverting output and a first non-inverting output;

a second operational amplifier having a second inverting input, a second non- inverting input, a second inverting output and a second non-inverting output, wherein the second inverting output communicates with the first non-inverting input and the second non-inverting output communicates with the first inverting input;

a first feedback element that communicates with the first non-inverting input and the first inverting output;

a second feedback element that communicates with the first inverting input and the first non-inverting output;

a third feedback element that communicates with the second inverting input and the first inverting output; and

a fourth feedback element that communicates with the second non-inverting input and the first non-inverting output,

wherein said first operational amplifier converts a current input signal to a voltage signal.

53. The transimpedance amplifier of claim 52 wherein said first operational amplifier generates said voltage signal;

wherein input of said second operational amplifier receives said current input signal, and

wherein the first and second operational amplifiers convert said current signal to said voltage signal.