Method and system for fast PLL close-loop settling after open-loop VCO calibration
First Claim
1. A method for signal processing, the method comprising:
- in a fractional-N phase-locked-loop (PLL) synthesizer comprising a phase-frequency detector (PFD), a loop filter, and a VCO,disabling of said PFD via a control signal and discharging said loop filter to ground via an unswitched leakage current, wherein said control signal is generated based on a received signal that indicates enabling an open-loop calibration of said VCO; and
subsequently enabling said PFD via said control signal when said received signal indicates a completion of said open loop calibration of said VCO and said received signal is triggered by an input reference signal thereby causing a phase of said input reference signal to lag a phase of a divider signal generated by a divider in said fractional-N PLL synthesizer.
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Abstract
Aspects of a method and system for a fast phase-locked loop (PLL) close-loop settling after an open-loop voltage controlled oscillator (VCO) calibration are provided. A fractional-N PLL synthesizer may comprise a VCO, a phase-frequency detector (PFD), a D flip-flop, a divider, a charge pump, and a loop filter. The synthesizer may disable the PFD based on a control signal indicating the start of VCO open-loop calibration. After open-loop calibration, the synthesizer may subsequently enable a PLL closed-loop settling and may enable the PFD to control the charge pump when the input reference signal phase lags a phase of a divider signal generated by the divider. The D flip-flop may enable and disable the PFD. During open-loop calibration, the loop filter may be discharged via a leakage current in the charge pump. During closed-loop settling, the loop filter may be charged by the charge pump via control of the PFD.
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Citations
20 Claims
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1. A method for signal processing, the method comprising:
in a fractional-N phase-locked-loop (PLL) synthesizer comprising a phase-frequency detector (PFD), a loop filter, and a VCO, disabling of said PFD via a control signal and discharging said loop filter to ground via an unswitched leakage current, wherein said control signal is generated based on a received signal that indicates enabling an open-loop calibration of said VCO; and subsequently enabling said PFD via said control signal when said received signal indicates a completion of said open loop calibration of said VCO and said received signal is triggered by an input reference signal thereby causing a phase of said input reference signal to lag a phase of a divider signal generated by a divider in said fractional-N PLL synthesizer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A system for signal processing, the system comprising:
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a fractional-N phase-locked-loop (PLL) synthesizer that comprises a phase-frequency detector (PFD), a loop filter, and a VCO; said fractional-N PLL synthesizer enables the disabling of said PFD via a control signal and discharging said loop filter to ground via an unswitched leakage current, wherein said control signal is generated based on a received signal that indicates enabling an open-loop calibration of said VCO; and said fractional-N PLL synthesizer subsequently enables the enabling of said PFD via said control signal when said received signal indicates a completion of said open loop calibration of said VCO and said received signal is triggered by an input reference signal thereby causing a phase of said input reference signal to lag a phase of a divider signal generated by a divider in said fractional-N PLL synthesizer. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification