Active pixel sensor with a diagonal active area
First Claim
Patent Images
1. A pixel cell of an imaging device, comprising:
- a photosensitive device for accumulating photo-generated charge having a generally S-shaped active area contacting a column output line;
a readout circuit comprising at least an output transistor;
said pixel cell being in a row of similar pixel cells in an array and sharing said column output line and said S-shaped active area with an adjacent pixel cell of the row; and
a first address circuit for the pixel cell and a second address circuit for the adjacent pixel cell, said first address circuit consisting of a first row select line and the column output line, and said second address circuit consisting of a second row select line and the column output line, said first and second row select lines being dedicated to the row and no other row.
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Abstract
An imaging device formed as a CMOS semiconductor integrated circuit having two adjacent pixels in a row connected to a common column line. By having adjacent pixels of a row share column lines, the CMOS imager circuit eliminates half the column lines of a traditional imager allowing the fabrication of a smaller imager. The imaging device also may be fabricated to have a diagonal active area to facilitate contact of two adjacent pixels with the single column line and allow linear row select lines, reset lines and column lines.
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Citations
21 Claims
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1. A pixel cell of an imaging device, comprising:
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a photosensitive device for accumulating photo-generated charge having a generally S-shaped active area contacting a column output line; a readout circuit comprising at least an output transistor; said pixel cell being in a row of similar pixel cells in an array and sharing said column output line and said S-shaped active area with an adjacent pixel cell of the row; and a first address circuit for the pixel cell and a second address circuit for the adjacent pixel cell, said first address circuit consisting of a first row select line and the column output line, and said second address circuit consisting of a second row select line and the column output line, said first and second row select lines being dedicated to the row and no other row. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An imager comprising:
a plurality of pixel cells, the pixel cells being arranged into an array of rows and columns, wherein two said pixel cells of a row are arranged such that they are linked by a generally S-shaped active area, each pixel cell being operable to generate a voltage at a diffusion node corresponding to detected light by the pixel cell, wherein the two said pixel cells lined by the generally S-shaped active area also share a common column line for addressing the two said pixel cells and the two said pixel cells are also addressed by an even row select line for one of the two said pixel cells and an odd row select line for the other of the two said pixel cells, said even and odd row select lines addressing the pixels of said row and no other row. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A CMOS imager array comprising:
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a plurality of CMOS imager pixels arranged in rows and columns in an array, at least one of said CMOS imager pixels having an active area having an S-shaped component connecting with a second one of the CMOS imager pixels of a same row; a plurality of column lines one of which being connected to the at least one of said CMOS imager pixels and the second one of the CMOS imager pixels, said column line being connected to output circuitry to output signals generated from detected light; an odd row select line configured to only address odd pixels in said same row, said at least one of said CMOS imager pixels being an odd pixel; an even row select line configured to only address even pixels in said same row, said second one of the CMOS imager pixels being an even pixel; and a first address circuit for the at least one of said CMOS imager pixels and a second address circuit for the second one of the CMOS imager pixels, said first address circuit consisting essentially of the odd row select line and the one column line, and said second address circuit consisting essentially of the even row select line and the one column line. - View Dependent Claims (18, 19, 20, 21)
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Specification