Active pixel sensor with a diagonal active area

• US 7,616,245 B2
• Filed: 05/07/2007
• Issued: 11/10/2009
• Est. Priority Date: 06/17/1999
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Rhodes, Howard E.
• Primary Examiner(s): Ho; Tuan V
• Assistant Examiner(s): BERARDESCA, PAUL M
• Application Number:
  US11/797,756
• Publication Number:
  US 20070205447A1
• Time in Patent Office: 918 Days
• Field of Search: 345/75.2, 250/208.1, 348/308
• US Class Current: 348/308
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14641 Electronic components shared by two or more pixel-elements, e.g. one amplifier shared by two pixel elements
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H04N 25/74 Circuitry for scanning or addressing the pixel array
• CPC Class Codes: H04N 3/1512 for MOS image-sensors, e.g. MOS-CCD H04N3/1581 takes precedence

Abstract

An imaging device formed as a CMOS semiconductor integrated circuit having two adjacent pixels in a row connected to a common column line. By having adjacent pixels of a row share column lines, the CMOS imager circuit eliminates half the column lines of a traditional imager allowing the fabrication of a smaller imager. The imaging device also may be fabricated to have a diagonal active area to facilitate contact of two adjacent pixels with the single column line and allow linear row select lines, reset lines and column lines.

Claims

1. A pixel cell of an imaging device, comprising:

a photosensitive device for accumulating photo-generated charge having a generally S-shaped active area contacting a column output line;

a readout circuit comprising at least an output transistor;

said pixel cell being in a row of similar pixel cells in an array and sharing said column output line and said S-shaped active area with an adjacent pixel cell of the row; and

a first address circuit for the pixel cell and a second address circuit for the adjacent pixel cell, said first address circuit consisting of a first row select line and the column output line, and said second address circuit consisting of a second row select line and the column output line, said first and second row select lines being dedicated to the row and no other row.

2. The pixel cell according to claim 1, wherein said photosensitive device is one of a photogate, a photodiode, or a photoconductor.

3. The pixel cell according to claim 1, further comprising a controllable charge transfer region having a control terminal, said transfer region being formed in a substrate adjacent said active area and having a node connected to a gate of said output transistor and at least one charge transfer device for transferring charge from said active area to said node in accordance with a control signal applied to said control terminal.

4. The pixel cell according to claim 3, wherein said charge transfer device is a field effect transistor.

5. The pixel cell according to claim 1, further comprising a straight column line formed of a metal layer in an integrated circuit to address said pixel cell.

6. The pixel cell according to claim 1, further comprising a reset transistor for resetting a node in response to a reset signal.

7. The pixel cell according to claim 6, wherein said reset transistor is addressed by a reset line which is substantially linear across the array.

8. The pixel cell according to claim 7, wherein said reset line is formed of a material selected from the group consisting of doped polysilicon, metals and refractory metal silicides.

9. The pixel cell according to claim 6, further comprising a row select transistor responsive to a row select signal to activate said pixel cell.

10. An imager comprising:

a plurality of pixel cells, the pixel cells being arranged into an array of rows and columns, wherein two said pixel cells of a row are arranged such that they are linked by a generally S-shaped active area, each pixel cell being operable to generate a voltage at a diffusion node corresponding to detected light by the pixel cell, wherein the two said pixel cells lined by the generally S-shaped active area also share a common column line for addressing the two said pixel cells and the two said pixel cells are also addressed by an even row select line for one of the two said pixel cells and an odd row select line for the other of the two said pixel cells, said even and odd row select lines addressing the pixels of said row and no other row.

11. The imager according to claim 10, further comprising:

a row select device connected to either said odd row select line or said even row select line respectively; and

a row decoder operable to activate the odd row select line and the even row select line by said row select device.

12. The imager according to claim 10, further comprising:

a reset device to reset the voltage of a diffusion node of one of the two said pixel cells;

a transfer device to transfer charge from said one of the two said pixel cells to said diffusion node; and

an output circuit connected to the common column line and being operable to store a voltage signal and to provide a sensor output signal.

13. The imager according to claim 10, wherein said pixel cells include a photogate, a photodiode or a photoconductor in said active area.

14. The imager according to claim 10, wherein said common column line is linear in said substrate.

15. The imager according to claim 12, wherein said reset device is addressed by a reset line which is linear in said substrate.

16. The imager according to claim 10, wherein said even and odd row select lines run substantially linearly across the array along the row.

17. A CMOS imager array comprising:

a plurality of CMOS imager pixels arranged in rows and columns in an array, at least one of said CMOS imager pixels having an active area having an S-shaped component connecting with a second one of the CMOS imager pixels of a same row;

a plurality of column lines one of which being connected to the at least one of said CMOS imager pixels and the second one of the CMOS imager pixels, said column line being connected to output circuitry to output signals generated from detected light;

an odd row select line configured to only address odd pixels in said same row, said at least one of said CMOS imager pixels being an odd pixel;

an even row select line configured to only address even pixels in said same row, said second one of the CMOS imager pixels being an even pixel; and

a first address circuit for the at least one of said CMOS imager pixels and a second address circuit for the second one of the CMOS imager pixels, said first address circuit consisting essentially of the odd row select line and the one column line, and said second address circuit consisting essentially of the even row select line and the one column line.

18. The CMOS imager array according to claim 17, wherein said column line is linear in said array.

19. The CMOS imager array according to claim 18, wherein said column line is formed of a metal.

20. The CMOS imager array according to claim 17, wherein said odd row select line and said even row select line are each substantially linear across said array.

21. The system according to claim 17, wherein said CMOS imager is part of a camera system, a scanner, a machine vision system, a vehicle navigation system or a video telephone system.