System to protect electrical fuses

• US 7,616,416 B2
• Filed: 08/16/2007
• Issued: 11/10/2009
• Est. Priority Date: 08/04/2004
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Jiann-Tseng, Chung, Shine, Huang, Shao-Chang
• Primary Examiner(s): DeBeradinis; Robert
• Assistant Examiner(s): BAUER, SCOTT ALLEN
• Application Number:
  US11/839,966
• Publication Number:
  US 20070279816A1
• Time in Patent Office: 817 Days
• Field of Search: 361/56, 327/525
• US Class Current: 361/56
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory

Abstract

A method and system is disclosed for protecting electrical fuse circuitry. A electrical fuse circuit with electrostatic discharge (ESD) protection has at least one electrical fuse, a programming device coupled in series with the electrical fuse having at least a transistor for receiving a control signal for controlling a programming current flowing through the electrical fuse, a voltage source coupled to the fuse and the programming device for providing the programming current, and a protection module coupled to a gate of the transistor at its first end for reducing charges accumulated at the gate of the transistor due to electric static charges arriving at the voltage source, thereby preventing the programming device from accidentally programming the fuse.

Claims

1. An electrical fuse circuit with electrostatic discharge (ESD) protection comprising:

at least one electrical fuse;

a programming device coupled in series with the electrical fuse having a first transistor for receiving a control signal for controlling a programming current flowing through the electrical fuse;

a voltage source coupled to the fuse and the programming device for providing the programming current;

a protection module comprising a zero threshold voltage transistor, a first end of the zero threshold voltage transistor coupled to a gate of the first transistor for reducing charges accumulated at the gate of the first transistor due to electric static charges arriving at the voltage source, thereby preventing the programming device from programming the fuse, and a second end of the zero threshold voltage transistor coupled to ground or VSS for diverting the charges accumulated; and

a driver coupled to a pre-driver protection circuit for providing the control signal, the pre-driver protection circuit including an NMOS transistor and a pull-up resistance device, the NMOS transistor configured to receive a programming signal at its gate, the resistance device being a gate-grounded PMOS device,

wherein the pre-driver protection circuit prevents an erroneous control signal from being generated during a power on process, thereby preventing the fuse from accidentally being programmed by the erroneous control signal, and wherein the electrical fuse is sized such that when high voltage is applied during the programming stage, the programming device is turned on and a programming current can flow through and break the fuse.

2. The circuit of claim 1, wherein the programming device is an NMOS device.

3. The circuit of claim 1, wherein a source and a drain of the programming device are respectively connected to ground or VSS and one end of the electrical fuse, and the other end of the electrical fuse being connected to the voltage source.

4. The circuit of claim 1 further comprising a voltage source clamping module coupled to the voltage source for clamping a voltage to a predetermined voltage value during an ESD event.

5. The circuit of claim 4, wherein the voltage source clamping module is a reverse-biased clamp diode, whose anode end is connected to ground or VSS and whose cathode end is connected to the voltage source.

6. The circuit of claim 4, wherein the voltage source clamping module is a forward-biased diode string having one or more diodes connected together in series, the anode and cathode ends of the clamping module connected respectively to the voltage source and ground or VSS, and wherein the number of the diodes in the diode string determines the clamped voltage.

7. The circuit of claim 1, wherein the driver is an inverter and the pre-driver protection circuit is coupled in series with an input of the driver coupled to a node between the resistance device and the NMOS device, wherein while programming the fuse, the NMOS device pulls the input to ground or VSS, and during a power up process when the NMOS device is floating, the resistance device protects the driver from accidentally providing a high control signal.

8. The circuit of claim 1, further comprising a parasitic discharge protection module coupled between the voltage source and the fuse for creating an RC parasitic discharge path between the voltage source and ground or VSS.

9. The circuit of claim 8, wherein the parasitic discharge protection module is a pass-gate.

10. The circuit of claim 1, further comprising a state machine protection module coupled to a fuse macro having a finite state machine whose output and a program control signal together trigger the fuse macro to be programmed, wherein the finite state machine, upon detecting a predetermined bit sequence, provides a predetermined output for triggering the fuse in the fuse macro to be programmed.

11. The circuit of claim 1, further comprising a security protection module having a security fuse cell to be coupled to a fuse array containing the fuse, wherein an output of the security protect ion module based on a programming state thereof determines whether the fuse array is to be programmed.

12. An electrical fuse circuit with electrostatic discharge (ESD) protection comprising:

at least one electrical fuse;

a programming device coupled in series with the electrical fuse having a transistor for receiving a control signal for controlling a programming current flowing through the electrical fuse;

a driver coupled to a pre-driver protection circuit for providing the control signal, wherein the driver is an inverter and the pre-driver protection circuit has a pull-up resistance device and a NMOS device coupled in series with an input of the driver coupled to a node between the resistance device and the NMOS device, wherein while programming the fuse, the NMOS device pulls the input to ground or VSS, and during a power up process when the NMOS device is floating, the resistance device includes a gate grounded PMOS device for protecting the driver from providing a high control signal;

a voltage source coupled to the fuse and the programming device for providing the programming current; and

a protection module coupled to a gate of the transistor at the first end of the transistor for reducing charges accumulated at the gate of the transistor due to electric static charges arriving at the voltage source,

wherein the protection module prevents the programming device from accidentally programming the fuse, the pre-driver protection circuit prevents an erroneous control signal from being generated during a power on process; and

the driver is sized to ensure that the control signal has a short transition rise time from low to high such that the electrical fuse can be programmed effectively.

13. The circuit of claim 12, further comprising a voltage source clamping module coupled to the voltage source for clamping a voltage thereon to a predetermined voltage value during an ESD event.

14. The circuit of claim 13, wherein the voltage source clamping module is a reverse-biased clamp diode, the anode end of the reverse-biased clamp diode is connected to ground or VSS and the cathode end of the reverse-biased clamp diode is connected to the voltage source.

15. The circuit of claim 13, wherein the voltage source clamping module is a forward-biased diode string having one or more diodes connected together in series, with the anode and cathode ends of the diodes connected respectively to the voltage source and ground or VSS, wherein the number of the diodes in the diode string determines the clamped voltage.