Multi-state memory cell with asymmetric charge trapping
First Claim
1. A method for programming a multi-state NAND memory cell having a control gate, first and second active areas, and a single, continuous nitride trapping layer formed at least a length of the control gate and configured for asymmetrical trapping near each of the active areas, the method comprising:
- applying a negative gate voltage, in a range of −
10V to −
15V, to the control gate;
grounding the second active area; and
applying a positive voltage to the first active area to inject an asymmetric distribution hole by gate induced drain leakage injection into the single, continuous nitride trapping layer substantially adjacent the first active area.
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Accused Products
Abstract
A multi-state NAND memory cell includes two drain/source areas in a substrate. An oxide-nitride-oxide structure is formed above the substrate between the drain/source areas. The nitride layer acting as an asymmetric charge trapping layer. A control gate is located above the oxide-nitride-oxide structure. An asymmetrical bias on the drain/source areas causes the drain/source area with the higher voltage to inject an asymmetric distribution hole by gate induced drain leakage injection into the trapping layer substantially adjacent that drain/source area.
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Citations
11 Claims
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1. A method for programming a multi-state NAND memory cell having a control gate, first and second active areas, and a single, continuous nitride trapping layer formed at least a length of the control gate and configured for asymmetrical trapping near each of the active areas, the method comprising:
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applying a negative gate voltage, in a range of −
10V to −
15V, to the control gate;
grounding the second active area; andapplying a positive voltage to the first active area to inject an asymmetric distribution hole by gate induced drain leakage injection into the single, continuous nitride trapping layer substantially adjacent the first active area. - View Dependent Claims (2, 3)
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4. A method for programming a multi-state NAND memory cell having a control gate, first and second source/drain regions, and a single, continuous nitride trapping layer formed at least a length of the control gate and configured for asymmetrical trapping of first and second data bits near each of the source/drain regions, the method comprising:
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applying a voltage, in a range of −
10V to −
15V, to the control gate; andapplying asymmetrical voltages to the first and second source/drain regions to program the first and second data bits. - View Dependent Claims (5, 6, 7, 8, 9, 10, 11)
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Specification