Dynamic voltage adjustment for memory

• US 7,616,509 B2
• Filed: 07/13/2007
• Issued: 11/10/2009
• Est. Priority Date: 07/13/2007
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Davar, Sushama, Jew, Thomas, Qureshi, Qadeer A.
• Primary Examiner(s): Dinh; Son
• Assistant Examiner(s): NGUYEN, NAM THANH
• Application Number:
  US11/777,635
• Publication Number:
  US 20090016140A1
• Time in Patent Office: 851 Days
• Field of Search: 365/201, 365/226, 365/129
• US Class Current: 365/201
• CPC Class Codes: G11C 11/41 forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

A power supply voltage for a memory on an integrated circuit is dynamically adjusted during the operating of the memory. The operating of the memory includes powering the memory at a supply voltage. A test memory of the integrated circuit is concurrently powered while operating the memory. The test memory and the memory each include bit cells of a first bit cell configuration type. A voltage level of the supply voltage is adjusted, while operating the memory, based on the testing of the test memory. The voltage level is adjusted with external variations to assume a value that guarantees no failed operation of the memory but also accurately minimizes the supply voltage. The system and method may be implemented with any type of memory. The memory and test memory may be physically implemented either separated or interspersed on the integrated circuit.

Claims

1. A method of powering a memory comprising:

operating a memory of an integrated circuit, the operating a memory includes powering the memory at a supply voltage;

testing a test memory of the integrated circuit concurrently while operating the memory, the test memory and the memory each including bit cells of a first bit cell configuration type; and

adjusting a voltage level of the supply voltage, while operating the memory, based on the testing the test memory.

2. The method of claim 1 wherein:

the testing includes determining a minimum voltage level for powering the test memory in which the test memory passes testing; and

the adjusting includes providing the supply voltage at a voltage level based on the determining a minimum voltage level.

3. The method of claim 1 wherein the testing the test memory includes:

testing the test memory while powering the test memory at a plurality of voltage levels; and

determining a highest voltage level of the plurality of voltage levels that the test memory fails testing.

4. The method of claim 3 wherein:

the adjusting includes adjusting the supply voltage to a voltage level that is higher than the highest voltage level.

5. The method of claim 3 wherein the test memory is powered at a voltage level that is less than the voltage level of the supply voltage by a predetermined amount, wherein during the powering the test memory at a plurality of voltage levels, the memory is powered at a plurality of voltage levels.

6. The method of claim 1 wherein the testing includes:

writing a data pattern to the test memory;

reading a data unit from the test memory; and

comparing the data pattern with the data unit.

7. A method of powering a memory, comprising:

powering a memory of an integrated circuit at an operating voltage level;

testing for a first time, a test memory of the integrated circuit;

adjusting the operating voltage level to a first adjusted operating voltage level based on the testing for the first time;

powering the memory at the first adjusted operating voltage level after the adjusting for a first time;

testing for a second time, the test memory;

adjusting the first adjusted operating voltage level to a second adjusted operating voltage level based on the testing for a second time; and

powering the memory at the second adjusted operating voltage level after the adjusting the first adjusted operating voltage level.

8. The method of claim 7 wherein:

the testing for a first time includes powering the test memory at a first test voltage level based on the operating voltage level; and

the testing for a second time includes powering the test memory at a second test voltage level based on the first adjusted operating voltage level.

9. The method of claim 8 wherein:

the first test voltage level is a predetermined amount less that the operating voltage level; and

the second test voltage level is the predetermined amount less than the first adjusted operating voltage level.

10. The method claim 7 wherein:

if the testing for the first time indicates failure, the adjusting for the first time includes increasing the operating voltage level to the first adjusted operating voltage, where the first adjusted operating voltage level is greater than the operating voltage level.

11. The method claim 7 wherein:

if the testing for the first time does not indicate failure, the adjusting for the first time includes decreasing the operating voltage level to the first adjusted operating voltage, where the first adjusted operating voltage level is less than the operating voltage level.

12. The method of claim 7 wherein:

the testing for a first time includes testing the test memory while powering the test memory at a plurality of voltage levels and determining a first lowest voltage level of the plurality of voltage levels that the testing indicates passing, wherein the first adjusted operating voltage level is based on the first lowest voltage level; and

the testing for the second time includes testing the test memory while powering the test memory at a plurality of voltage levels and determining a second lowest voltage level of the plurality of voltage levels that the testing indicates passing, wherein the second adjusted operating voltage level is based on the second lowest voltage level.

13. A system comprising:

a memory of an integrated circuit, the memory including a supply terminal for receiving an operating supply voltage;

a test memory of the integrated circuit, the test memory including a test supply terminal for receiving a test supply voltage for powering the test memory, the test memory and the memory each including bit cells of a first bit cell configuration type; and

test circuitry coupled to the test memory for testing and determining performance of the test memory, the test circuitry operable for finding a lowest test supply voltage level received at the test supply terminal at which the test memory passes testing;

wherein the supply terminal of the memory is configured to receive the operating supply voltage that is adjustable during memory operation based on performance of the test memory as determined by the test circuitry.

14. The system of claim 13 wherein the supply terminal of the memory is configured to receive the operating supply voltage at a voltage level that is at a predetermined amount above the minimum test supply voltage level.

15. The system of claim 13 wherein the test supply voltage is supplied at a voltage level less than a voltage level of the operating supply voltage by a predetermined amount.

16. The system of claim 13 wherein the operating supply voltage is increased based on a failed test of the test memory as determined by the test circuitry.

17. The system of claim 13 wherein the test circuitry tests the test memory with the test supply terminal being supplied at a first test voltage level that is based on the operating supply voltage at a first voltage level, wherein the operating supply voltage is lowered to a second voltage level based upon a determination that the test memory passes testing while being supplied at the first test voltage level.

18. The system of claim 17 wherein the operating supply voltage is lowered to the second voltage level based upon a determination that the test memory consecutively passes a predetermined number of tests while being supplied at the first test voltage level.

19. The system of claim 13 wherein the test circuitry tests the test memory with the test supply terminal being supplied at a test voltage level that is based on the operating supply voltage at a first voltage level, wherein the operating supply voltage is raised to a second voltage level based upon a determination that the test memory fails testing while being supplied at the first test voltage level.

20. The system of claim 19 further comprising a voltage adjustment circuit for supplying the test supply voltage at a plurality of voltage levels, wherein the test circuitry tests the test memory at levels of the plurality of voltage levels to determine a lowest voltage level of the plurality of voltage levels that allows the test memory to pass testing, the operating supply voltage is supplied at a voltage level based on the lowest voltage level determined to allow the test memory to pass testing.

21. The system of claim 13 further comprising:

a voltage regulator including an output coupled to the supply terminal and an input coupled to the test circuitry to receive an indication for adjusting the operating supply voltage based on performance of the test memory as determined by the test circuitry.