Monolithic GPS RF front end integrated circuit

• US 7,616,705 B1
• Filed: 07/26/2001
• Issued: 11/10/2009
• Est. Priority Date: 07/27/2000
• Status: Expired due to Fees

• Current Assignee: CSR Technology Incorporated (Qualcomm, Inc.)
• Original Assignee: SiRF Technology Holdings Incorporated (Qualcomm, Inc.)
• Inventors: Tso, Robert, McConnell, Richard Joseph
• Primary Examiner(s): Corrielus; Jean B
• Application Number:
  US09/916,087
• Time in Patent Office: 3,029 Days
• Field of Search: 340/426.19, 342/357.12, 455/404.2, 455259-260, 455/150.1, 375/136, 375/150, 375/147, 375/343, 375/316
• US Class Current: 375/316
• CPC Class Codes: G01S 19/36 relating to the receiver frond end
• CPC Class Codes: H03L 2207/10 Indirect frequency synthesis using a frequency multiplier in the phase-locked loop or in the reference signal path
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H04L 27/36 Modulator circuits; Transmitter circuits

Abstract

A highly integrated GPS RF Front End, an interface thereto, and a GPS receiver that incorporates the GPS RF front end, which uses a single conversion stage employing an image rejection mixer stage to eliminate the need for an image reject RF bandpass filter. Also a relatively high sample rate A/D is employed which allows a timeless monolithic IF Filter to be used. The disclosure also discusses a GPS Front End topology that is easily integrated from industry standard building blocks. With the broad variation in potential receiver designs, the present invention includes some specific receiver topologies that lend themselves to a high level of integration. The specific designs presented here are comprised of industry standard building blocks and functions that have been described elsewhere in the related art.

Claims

1. A Global Positioning System (GPS) receiver, comprising:

a Radio Frequency (RF) Front End, comprising;

a single stage downconverter using dual mixers that downconverts a received GPS signal;

an I/Q Intermediate Frequency (IF) active filter, coupled to the downconverter;

an Automatic Gain Control (AGC) amplifier, coupled to the downconverter;

an Analog-to-Digital Converter (ADC) coupled to the AGC amplifier; and

a frequency synthesizer section including an integrated Voltage Controlled Oscillator and a reference oscillator with a frequency of 24.5535 MHz plus or minus 40 parts per million (ppm), and further comprising;

a frequency doubler coupled to the reference oscillator;

a divide-by-9 circuit coupled to the frequency doubler;

a phase and frequency detector (PFD) coupled to the divide-by-9 circuit;

a charge pump coupled between the PFD and the VCO;

the voltage controller oscillator (VCO) that is also coupled to the downconverter;

a divide-by-41 circuit coupled to the VCO; and

a divide-by-7 circuit coupled between the divide-by-41 circuit and the PFD to make a phase locked loop; and

a digital processing section, coupled to the RF Front End, wherein the noise bandwidth of the GPS receiver is set by the IF active filter.

2. The GPS receiver of claim 1 wherein the reference oscillator is adapted for receiving an external reference signal.

3. The GPS receiver of claim 1 further comprising a crystal for providing an external reference signal to the reference oscillator.

4. The GPS receiver of claim 1, wherein output interface signals of the RF Front End are Positive Emitter Collector Logic (PECL) compatible.

5. The GPS receiver of claim 4, wherein the PECL compatible outputs of the RF Front End further include an acquisition clock (ACQCLK) signal generated by the frequency synthesizer section.

6. The GPS receiver of claim 4, wherein the ACQCLK signal has a frequency approximately equal to 37.3333fo, where fo=1.023 MHz.

7. The GPS receiver of claim 6, wherein the PECL compatible outputs further include a GPS clock (GPSCLK) signal output from the frequency synthesizer section.

8. The GPS receiver of claim 7, wherein the GPSCLK signal has a frequency approximately equal to 48fo, where fo=1.023 MHz.

9. The GPS receiver of claim 1, comprising an external antenna assembly coupled to the RF front end.

10. The GPS receiver of claim 9 wherein the external antenna assembly comprises an antenna coupled to a low noise amplifier (LNA), and a radio frequency (RF) bandpass filter coupled to the LNA.

11. The GPS receiver of claim 1 wherein the synthesizer comprises an external loop filter coupled to the VCO.

12. The GPS receiver of claim 1 the RF front end further comprising an I/Q combiner circuit coupled to the IF active filter for combining filtered I-IF and Q-IF outputs received therefrom and outputting a single IF output signal to the AGC amplifier.