Conductive DC biasing for capacitively coupled on-chip drivers

• US 7,616,926 B2
• Filed: 12/27/2006
• Issued: 11/10/2009
• Est. Priority Date: 12/27/2006
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Drost, Robert J.
• Primary Examiner(s): Nguyen; Duc M
• Application Number:
  US11/647,060
• Publication Number:
  US 20080159412A1
• Time in Patent Office: 1,049 Days
• Field of Search: 455/41.1, 455/67.11, 455/67.13, 455/295, 455/296, 455/310, 326/21, 326/30, 326/31, 326/34, 327/362
• US Class Current: 455/41.1
• CPC Class Codes: H04L 25/026 Arrangements for coupling transmitters, receivers or transceivers to transmission lines; Line drivers duplexing arrangements H04L5/14
• CPC Class Codes: H04L 25/0284 Arrangements to ensure DC-balance

Abstract

An integrated circuit containing a communication channel is described. This communication channel includes: a transmit circuit configured to transmit signals; a link coupled to an output of the transmit circuit; a receive circuit coupled to the link; and a clamping circuit coupled to the link. Note that the transmit circuit is capacitively coupled to the receive circuit via the link. Furthermore, the clamping circuit is configured to compensate for leakage current on the link by maintaining a voltage on the link corresponding to a logical “1” or a logical “0.” This voltage is based on a history of the transmitted signals.

Claims

1. An integrated circuit containing a communication channel, wherein the communication channel comprises:

a transmit circuit configured to transmit signals;

a link coupled to an output of the transmit circuit;

a receive circuit coupled to the link, wherein the transmit circuit is capacitively coupled to the receive circuit via the link; and

a clamping circuit coupled to the link, wherein the clamping circuit is configured to compensate for leakage current on the link by maintaining a voltage on the link corresponding to a logical “

1”

or a logical “

0”

, and wherein the voltage is based on a history of the transmitted signals.

2. The integrated circuit of claim 1, wherein the transmit circuit includes a voltage-mode driver or a current-mode driver.

3. The integrated circuit of claim 1, wherein the clamping circuit sets a DC bias voltage of the link.

4. The integrated circuit of claim 1, wherein the clamping circuit includes a conductive driver in parallel with the link.

5. The integrated circuit of claim 1, wherein the clamping circuit is configured to disable the conductive driver for a given signal type in the transmitted signals, and wherein the given signal type corresponds to one of the logical “

1” and

the logical “

0”

.

6. The integrated circuit of claim 5, wherein the transmitted signals are constrained to include a signal transition within a pre-determined time interval from a previous signal transition.

7. The integrated circuit of claim 1, wherein the clamping circuit has an RC time-constant that is greater than a time-constant of a transient characteristic of the transmitted signals;

wherein R is a resistance of a conductive path in the clamping circuit, and C is a total capacitance of the link; and

wherein the transient characteristic provides pre-emphasis to the receive circuit.

8. The integrated circuit of claim 1, wherein the clamping circuit is configured to disable the conductive driver for times less than a specified time interval, and to enable the conductive driver for times greater than the specified time interval.

9. The integrated circuit of claim 8, wherein the specified time interval corresponds to a transient characteristic of the transmitted signals, and wherein the transient characteristic provides pre-emphasis to the receive circuit.

10. The integrated circuit of claim 8, wherein the specified time interval of the clamping circuit is configured to be set using an adjustable delay element that has discrete time delays.

11. The integrated circuit of claim 8, wherein the specified time interval of the clamping circuit is configured to be set using an adjustable delay element that has continuous time delays.

12. The integrated circuit of claim 8, wherein the clamping circuit is configured to maintain the voltage for times longer than the specified time interval.

13. The integrated circuit of claim 1, wherein a frequency response of the communication channel is approximately uniform from DC up to a frequency.

14. The integrated circuit of claim 1, further including control logic, wherein the control logic is configured to adjust a frequency response of the clamping circuit.

15. The integrated circuit of claim 14, wherein the control logic is configured to adjust the frequency response after a pre-determined time interval has passed since a last adjustment.

16. The integrated circuit of claim 14, wherein the control logic is configured to adjust the frequency response continuously.

17. The integrated circuit of claim 1, wherein the integrated circuit has an approximately constant latency when communicating data via the link.

18. The integrated circuit of claim 1, wherein the receive circuit includes a single-ended amplifier or a differential amplifier.

19. A computer system, comprising:

a processor;

memory, wherein the memory is configured to store one or more program module mechanisms; and

an integrated circuit containing a communication channel, wherein the communication channel includes;

a transmit circuit configured to transmit signals;

a link coupled to an output of the transmit circuit;

a receive circuit coupled to the link, wherein the transmit circuit is capacitively coupled to the receive circuit via the link; and

a clamping circuit coupled to the link, wherein the clamping circuit is configured to compensate for leakage current on the link by maintaining a voltage on the link corresponding to a logical “

1”

or a logical “

0”

, and wherein the voltage is based on a history of the transmitted signals.

20. A method for maintaining a voltage on a link in an integrated circuit, comprising:

transmitting signals on a communication channel in the integrated circuit using a transmit circuit, wherein the communication channel includes a capacitively coupled link between the transmit circuit and a receive circuit;

receiving the transmitted signals through the receive circuit; and

maintaining a voltage on the link to compensate for leakage current on the link, wherein the voltage corresponds to a logical “

1”

or a logical “

0”

, and wherein the voltage is based on a history of the transmitted signals.