Refresh port for a dynamic memory

• US 7,617,356 B2
• Filed: 12/31/2002
• Issued: 11/10/2009
• Est. Priority Date: 12/31/2002
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Bains, Kuljit S.
• Primary Examiner(s): Chace; Christian P
• Assistant Examiner(s): RUTZ, JARED IAN
• Application Number:
  US10/334,374
• Publication Number:
  US 20040128433A1
• Time in Patent Office: 2,506 Days
• Field of Search: 711/105, 711/106, 711/5, 365/185.25, 365/222
• US Class Current: 711/106
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays

Abstract

A refresh port for a dynamic memory. In one embodiment, an apparatus includes a memory and a refresh command interface to receive a refresh command including a portion indicating signal. Refresh logic performs a refresh to a portion of the memory array specified, at least partially, by the portion specifying signal. Data transfer interfaces receive data transfer commands and transfer memory to and from the apparatus. Another apparatus includes refresh control logic to output a refresh signal and a portion specifying signal via a refresh command interface.

Claims

1. A memory device comprising:

a dynamic random access memory (DRAM);

a data transfer port coupled to the DRAM to receive data transfer requests and memory addresses from an external memory controller;

a refresh port coupled to the DRAM to receive refresh commands from the external memory controller, wherein the external memory controller includes a memory request logic to transmit said data transfer requests and memory addresses to the memory device and refresh control logic to provide said refresh commands and to inhibit memory access commands during a refresh, and wherein the external memory controller schedules refreshes to different memory locations than the data transfer requests, and schedules data transfer requests to different memory locations than the refresh requests to reduce interference with the data transfer requests by coordinating the data transfer requests from the memory request logic with the refresh commands from the refresh control logic by throttling a rate of memory requests to a portion of the DRAM needing additional refreshes.

2. The memory device of claim 1 wherein said refresh port is a dedicated port that is dedicated to performing refresh related functions.

3. The memory device of claim 1 wherein the refresh port comprises:

a plurality of portion-indicating interfaces;

a refresh command interface.

4. The memory device of claim 3 wherein the refresh port is an input port further comprising:

logic to receive a bank indicating signal via the plurality of portion-indicating interfaces;

logic to receive a refresh command from the refresh command interface.

5. The memory device of claim 3 wherein said plurality of portion-indicating interfaces comprise a plurality of bank number interfaces to specify a row for refreshing by specifying one of a plurality of banks, wherein a row number is automatically generated.

6. A memory device comprising:

a memory array;

a refresh command interface to receive refresh commands from a memory controller, the refresh commands each including a portion specifying signal wherein the refresh command interface throttles a rate of memory requests to a portion of the memory array needing additional refreshes;

refresh logic to refresh a portion of said memory array specified by the portion specifying signals in response to the refresh commands;

a plurality of data transfer interfaces to receive data transfer commands from the memory controller, and to transfer memory data to and from the memory device, wherein the memory controller prevents scheduling the refresh commands and the data transfer commands to a same location within the memory array to reduce interference with the transfer of memory data without having to provide separate data transfer and refresh bit-lines for each location in the memory array.

7. The memory device of claim 6 wherein said refresh command interface comprises:

a plurality of portion-specifying interfaces to receive said portion specifying signal that specifies a portion of the memory array to be refreshed;

a refresh interface to receive a refresh signal.

8. The memory device of claim 7 wherein said memory array comprises a plurality of banks, further comprising:

a plurality of bank refresh counters, one of the plurality of bank refresh counters being associated with each one of said plurality of banks, wherein said portion specifying signal specifies a bank, and wherein a refresh counter associated with the bank specifies a row within the bank.

9. The memory device of claim 8 wherein in response to the refresh signal, the refresh logic refreshes the row in the bank specified by the portion specifying signal and alters a refresh counter value of the refresh counter associated with the bank.

10. The memory device of claim 9 wherein the refresh logic increments or decrements the refresh counter in response to the refresh signal.

11. The memory device of claim 6 wherein the plurality of data transfer interfaces comprises a plurality of data interfaces and a plurality of address interfaces.

12. An apparatus comprising:

a plurality of data transfer interfaces to output data transfer requests and to transfer memory data to and from the apparatus;

a refresh command interface to output refresh commands to a memory device;

refresh control logic to output a refresh signal and a portion specifying signal via the refresh command interface by throttling a rate of memory requests to a portion of the memory device needing additional refreshes;

a processor portion to execute a plurality of program instructions and to initiate a plurality of memory requests to be communicated via the plurality of data transfer interfaces, wherein the processor portion prevents scheduling the outputting of the refresh commands and the outputting of the data transfer requests to a same memory location in the memory device to reduce interference with the transfer of memory data without having to provide separate data transfer and refresh bit-lines for each location in the memory array; and

a cache control portion, said cache control portion coupled to the processor portion and coupled to the plurality of data transfer interfaces to generate the plurality of memory requests as cache accesses on the plurality of data transfer interfaces.

13. The apparatus of claim 12 wherein said portion specifying signal comprises bank specifying signals.

14. The apparatus of claim 13 further comprising:

refresh count logic, said refresh count logic to track refresh activity and to inhibit activity on said plurality of data transfer interfaces if a refresh metric is not met.

15. The apparatus of claim 13 wherein said apparatus comprises an integrated processor and memory controller.

16. The apparatus of claim 12 wherein said apparatus comprises machine readable data carried on a machine readable medium.

17. The apparatus of claim 12 wherein said apparatus comprises one or more of hardware, software, and firmware.

18. A method comprising:

providing commands from an external memory controller to a separate memory device that requires or benefits from refreshing, the commands including memory request commands and memory address signals that together define memory accesses, via an data transfer interface;

providing from the external memory controller to the separate memory device, refresh commands specifying portions to refresh of a memory array via a refresh port wherein the data transfer port is separate from the refresh port;

scheduling by the external memory controller the refresh commands and the memory request commands to different portions of the memory array to reduce interference with the memory accesses wherein the external memory controller transmits said cache memory requests to a selected portion of the cache memory device and inhibits memory access commands to the selected portion of the cache memory device during a refresh; and

scheduling, by the external memory controller, refreshes to different portions of the cache memory device to reduce interference with cache memory requests by coordinating data transfer requests with said refresh commands by throttling a rate of memory request to the selected portion of the cache memory.

19. The method of claim 18 wherein providing refresh commands further comprises:

asserting a refresh signal;

providing a plurality of portion indicating signals.

20. The method of claim 19 further comprising:

tracking refresh activity;

inhibiting memory requests in response to said tracking if a refresh metric is not met.

21. The method of claim 19 wherein said refresh port is a dedicated refresh port separate from said command interface.

22. The method of claim 21 wherein said plurality of portion indicating signals comprise a plurality of bank indicating signals.

23. The method of claim 22 further comprising:

providing commands defining a memory access and providing a refresh command both being at least partially performed during a clock cycle.

24. A system comprising:

a first device having a memory request interface and a refresh output port;

a memory device comprising a memory array, the memory device being coupled to the first device, the memory array having a refresh input port coupled to the refresh output port, the memory device to refresh memory cells at least partially specified by refresh commands in response to refresh commands received from the first device via the refresh output port and the refresh input port, wherein said first device is a processor comprising a cache controller to communicate with the memory device, wherein the memory device is treated as a cache memory by the cache controller and the first device is to generate a plurality of portion-specifying signals transferred to the memory device via the refresh output port and the refresh input port, further wherein the cache controller transmits the cache memory requests to the cache memory device and inhibits memory access commands during a refresh and throttles a rate of memory request to a portion of the cache memory needing additional refreshes.

25. The system of claim 24 wherein said first device memory controller is to generate a refresh signal that is transferred to the memory device via the refresh output port and the refresh input port.

26. The system of claim 25 wherein said memory device further comprises a plurality of memory banks, wherein each bank has an associated row counter, and wherein said memory devices refreshes a row in a bank indicated by said plurality of bank indicating signals and adjusts the associated row counter in response to the refresh signal.

27. The system of claim 26 wherein said first device memory controller further comprises a refresh timing supervisor comprising a plurality of timers each associated with one of the plurality of memory banks, wherein the refresh timing supervisor is to reduce accesses to a memory bank if an associated one of said plurality of timers indicates a potential refresh shortage.

28. The system of claim 24 wherein said plurality of portion-specifying signals comprises a plurality of bank indicating signals.

29. The system of claim 24 further comprising a network interface.