Memory system including a two-on-one link memory subsystem interconnection
First Claim
1. A memory system comprising:
- a first memory subsystem comprising;
a buffer device having a first port, a second port, and a third port;
one or more memory devices coupled to the buffer device via the second port;
a first two-on-one link for coupling to a memory controller for providing communication between the buffer device and the memory controller, the first two-on- one link coupled to the first port of the buffer device, the first memory subsystem configured to transfer data between at least one memory device of the one or more memory devices and the memory controller via the buffer device and the first two-on-one link, wherein the first two-on-one link comprises up to two transceivers connected to a single link, wherein at least one of the up to two transceivers consists of two or more transmitters on a single chip die connected to a single chip die output pad for transmitting signals via the single chip die output pad over the single;
a second buffer device having a first port and a second port;
a second two-on-one link having a first connection to the third port of the buffer device and a second connection to the first port of the second buffer device; and
one or more second memory devices connected to the second port of the second buffer device, wherein the memory subsystem is further configured to transfer data between at least one memory device of the one or more second memory devices and the memory controller via a path comprising the buffer device, the first two-on-one link, the second buffer device and the second two-on-one link.
1 Assignment
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Accused Products
Abstract
A memory system including a first memory subsystem having a buffer device with a first port and a second port, one or more memory devices coupled to the buffer device via the second port, and a first two-on-one link for coupling to a memory controller for providing communication between the buffer device and the memory controller. The first two-on-one link is coupled to the first port of the buffer device. The first memory subsystem is configured to transfer data between at least one memory device of the one or more memory devices and the memory controller via the buffer device. The first two-on-one link includes up to two transceivers connected to a single link, with at least one of the up to two transceivers consisting of any one of two or more transmitters for transmitting signals or two or more receivers for receiving signals.
26 Citations
21 Claims
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1. A memory system comprising:
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a first memory subsystem comprising; a buffer device having a first port, a second port, and a third port; one or more memory devices coupled to the buffer device via the second port; a first two-on-one link for coupling to a memory controller for providing communication between the buffer device and the memory controller, the first two-on- one link coupled to the first port of the buffer device, the first memory subsystem configured to transfer data between at least one memory device of the one or more memory devices and the memory controller via the buffer device and the first two-on-one link, wherein the first two-on-one link comprises up to two transceivers connected to a single link, wherein at least one of the up to two transceivers consists of two or more transmitters on a single chip die connected to a single chip die output pad for transmitting signals via the single chip die output pad over the single; a second buffer device having a first port and a second port; a second two-on-one link having a first connection to the third port of the buffer device and a second connection to the first port of the second buffer device; and one or more second memory devices connected to the second port of the second buffer device, wherein the memory subsystem is further configured to transfer data between at least one memory device of the one or more second memory devices and the memory controller via a path comprising the buffer device, the first two-on-one link, the second buffer device and the second two-on-one link. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A memory subsystem comprising:
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one or more repeater devices; one or more two-on-one links, each two-on-one link having a first connection for connecting to a memory controller and a second connection connected to a respective repeater device of the one or more repeater devices, wherein the memory controller is connected to each respective repeater device via a respective two-on-one link; a plurality of repeater links, each repeater link having a first connection for connecting to a respective buffer device of a plurality of buffer devices and a second connection to the respective repeater device, wherein the memory subsystem is configured to transfer data between at least one memory device and the memory controller via a path comprising a buffer device, a repeater link, the respective repeater and the two-on-one link, wherein the two-on-one link comprises up to two transceivers connected to a single link, wherein at least one of the up to two transceivers consists of two or more transmitters on a single chip die connected to a single chip die output pad for transmitting signals via the single chip die output pad over the single; a first plurality of buffer devices, each buffer device of the first plurality of buffer devices having an interface connected to a respective one or more memory devices, each buffer device of the first plurality of buffer devices having a second interface connected to said respective repeater device via said respective repeater link; and a second plurality of buffer devices, each buffer device of the second plurality of buffer devices having an interface connected to a respective one or more second memory devices, and wherein each of said repeater links consist of a corresponding two-on-one link wherein each two-on-one link comprises up to two transceivers connected to a single link, wherein at least one of the up to two transceivers consists of any one of two or more transmitters on a single chip die connected to a single chip die output pad for transmitting signals via the single chip die output pad over the single link or two or more receivers on the single chip die connected to a single chip die input pad for receiving signals via the single chip die input pad from the single link. - View Dependent Claims (10, 11, 12)
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13. A computer memory subsystem method comprising:
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a memory controller receiving data from a buffer device at a memory subsystem port on a memory controller having a plurality of memory subsystem ports, the data received via a two-on-one link coupled to the buffer device, the buffer device having a first port coupled to one or more memory devices and a second port coupled to the two-on-one link wherein the data received at the memory controller is transferred from at least one of the memory devices to the memory controller via the buffer device and the two-on-one link, wherein the two-on-one link comprises up to two transceivers connected to a single link, wherein at least one of the up to two transceivers consists of two or more transmitters on a single chip die connected to a single chip die output pad for transmitting signals via the single chip die output pad over the single link; transmitting data from the memory subsystem port on the memory controller to the first port on the buffer device via the two-on-one link; the at least one of the transceivers performs a function consisting of any one of receiving data by way of two receivers or transmitting data by way of a selected one of said two transmitters, and wherein the buffer device further includes a third port in communication with a second buffer device via a second two-on-one link, the second buffer device having a first port coupled to one or more second memory devices and a second port coupled to the second two-on-one link comprising the further step of transferring data between one or more of the second memory devices and the memory controller via the second two-on-one link, the buffer device and the two-on-one link wherein the second two-on-one link comprises up to two transceivers connected to a single link, wherein at least one of the up to two transceivers consists of any one of two or more transmitters on a single chip die connected to a single chip die output pad for transmitting signals via the single chip die output pad over the single link or two or more receivers on the single chip die connected to a single chip die input pad for receiving signals via the single chip die input pad from the single link. - View Dependent Claims (14, 15, 16)
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17. A computer memory subsystem method comprising:
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a repeater device comprising a two-on-one link and a plurality of repeater links, the repeater device receiving first data from one of said repeater links and transmitting the first data to said two-on-one link; the repeater device receiving second data from said two-on-one link and transmitting the second data to one of said repeater links, wherein the two-on-one link comprises up to two transceivers connected to a single link, wherein at least one of the up to two transceivers consists of two or more transmitters on a single chip die connected to a single chip die output pad for transmitting signals via the single chip die output pad over the single link, wherein the at least one of the transceivers performs a function consisting of transmitting data by way of a selected one of said two transmitters; a first plurality of buffer devices, each buffer device of the first plurality of buffer devices having an interface connected to a respective one or more memory devices, each buffer device of the first plurality of buffer devices having a second interface connected to said respective repeater device via said respective repeater link, the repeater device receiving the first data from the first plurality of buffer devices via one of the repeater links; a second plurality of buffer devices, each buffer device of the second plurality of buffer devices having an interface connected to a respective one or more second memory devices, the repeater device receiving the first data from the first plurality of buffer devices via one of the repeater links; and wherein each of the repeater links consist of a corresponding two-on-one link wherein each two-on-one link of the repeater links comprises up to two transceivers connected to a single link, wherein at least one of the up to two transceivers consists of any one of two or more transmitters on a single chip die connected to a single chip die output pad for transmitting signals via the single chip die output pad over the single link or two or more receivers on the single chip die connected to a single chip die input pad for receiving signals via the single chip die input pad from the single link. - View Dependent Claims (18, 19, 20)
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21. A memory system comprising:
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a controller device; a first buffer device having a first interface, a second interface, and a third interface; a second buffer device having a first interface and a second interface; a first two-on-one link having a first connection to the controller device and a second connection to the first interface of the first buffer device; a first plurality of memory devices connected to the second interface of the first buffer device; a second two-on-one link having a first connection to the controller device and a second connection to the first interface of the second buffer device; a second plurality of memory devices connected to the second interface of the second buffer device wherein each two-on-one link comprises up to two transceivers connected to a single link, wherein at least one of the up to two transceivers consists of two or more transmitters on a single chip die connected to a single chip die output pad for transmitting signals via the single chip die output pad over the single link; a third buffer device having a first interface and a second interface; a third two-on-one link having a first connection to the third interface and a second connection to the first interface of the third buffer device; and a third plurality of memory devices connected to the second interface of the third buffer device.
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Specification