Method and apparatus for accessing a memory
First Claim
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1. A memory access mechanism for a node, comprising:
- an upper layer protocol;
a translation page table for storing data corresponding to a plurality of memory regions in the node; and
a plurality of steering tags that are controlled by the upper layer protocol, wherein the plurality of steering tags and resources to support the steering tags are allocated to the upper layer protocol that is part of the node prior to a latency sensitive operation, the upper layer protocol assigning at least one of the plurality of steering tags to be associated with at least one of the plurality of memory regions for a memory operation, wherein the assigning is performed in direct response to a request by a consumer.
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Abstract
The disclosed embodiments relate to an optimized memory registration mechanism that may comprise an upper layer protocol that associates I/O buffers with memory regions and that manages steering tags. The memory regions may be associated with a translation page table. The upper layer protocol may allocate one of the steering tags associated with at least one of the memory regions for a memory operation.
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Citations
20 Claims
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1. A memory access mechanism for a node, comprising:
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an upper layer protocol; a translation page table for storing data corresponding to a plurality of memory regions in the node; and a plurality of steering tags that are controlled by the upper layer protocol, wherein the plurality of steering tags and resources to support the steering tags are allocated to the upper layer protocol that is part of the node prior to a latency sensitive operation, the upper layer protocol assigning at least one of the plurality of steering tags to be associated with at least one of the plurality of memory regions for a memory operation, wherein the assigning is performed in direct response to a request by a consumer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A first computer system for communication with a second computer system, comprising:
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a consumer and at least one input/output device; wherein the at least one input/output device comprises a memory access mechanism, the memory access mechanism comprising; a plurality of buffers associated with the consumer; and a plurality of steering tags that are managed by the consumer, wherein the consumer is to issue a request to cause allocation of one of the plurality of steering tags to be associated with at least one of the plurality of buffers for a memory access operation, wherein the request is issued to cause allocation of the one steering tag prior to start of the memory access operation that is latency sensitive. - View Dependent Claims (11, 12, 13)
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14. A method for providing access to a memory, the method comprising the acts of:
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allocating, by a mechanism in a first node, a plurality of steering tags to an upper layer protocol in the first node, wherein allocating the plurality of steering tags occurs prior to a latency sensitive operation; allocating a plurality of buffers associated with the upper layer protocol, wherein the plurality of buffers are part of the first node; issuing command to a remote direct memory access network interface card in the first node after the allocation of the plurality of steering tags has been completed; associating one of the steering tags to at least one of the plurality of buffers once a command is received at the upper layer protocol which associates buffer information that describes the at least one of the plurality of buffers associated with the one of the plurality of steering tags; and advertising the one of the plurality of steering tags without waiting for the association to return a value. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification