Error monitoring for serial links

• US 7,617,424 B2
• Filed: 12/30/2005
• Issued: 11/10/2009
• Est. Priority Date: 12/30/2005
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Dabral, Sanjay, Navada, Muraleendhara, Frodsham, Timothy, Schoenborn, Zale T.
• Primary Examiner(s): Chung; Phung M
• Application Number:
  US11/323,111
• Publication Number:
  US 20070157054A1
• Time in Patent Office: 1,411 Days
• Field of Search: 714/704, 714/706, 714/797, 714/799, 714/812, 714/705, 377/49, 377/94, 377/26, 377/44, 377/55
• US Class Current: 714/704
• CPC Class Codes: H04L 1/242 by comparing a transmitted test signal with a locally generated replica

Abstract

Methods, apparatuses and systems for physical link error data capture and analysis.

Claims

1. An apparatus comprising:

a plurality of N-bit counters each coupled with a plurality of receivers coupled with corresponding serial data links;

a multiplexer coupled with the plurality of N-bit counters to select an output signal from one of the plurality of N-bit counters; and

an expanded counter coupled with the output of the multiplexer to count output signals from the multiplexer.

2. The apparatus of claim 1 wherein the N-bit counters comprise 8-bit counters.

3. The apparatus of claim 1 wherein the N-bit counters are coupled to count errors detected on the respective serial links.

4. The apparatus of claim 1 further comprising a register coupled to store a value based, at least in part, on a selected N-bit counter and the expanded counter.

5. A system comprising:

a plurality of test registers;

a port to communicate via a point-to-point serial link having a receiver and a control circuit coupled with the receiver, the control circuit having a plurality of N-bit counters each coupled with a serial data link, a multiplexer coupled with the plurality of N-bit counters to select an output signal from one of the plurality of N-bit counters, and an expanded counter coupled with the output of the multiplexer to count output signals from the multiplexer, the control circuit coupled with the plurality of test registers.

6. The system of claim 5 wherein the N-bit counters comprise 8-bit counters.

7. The system of claim 5 wherein the N-bit counters are coupled to count errors detected on the respective serial links.

8. The system of claim 5 further comprising a register coupled to store a value based, at least in part, on a selected N-bit counter and the expanded counter.

9. A method comprising:

counting bit errors detected in a plurality of data streams received via a plurality of point-to-point serial links using a plurality of corresponding N-bit counters; and

selectively enabling a multiplexer to pass output signals from the plurality of N-bit counters to an expanded counter to expand counting capacity utilizing the extended counter to enable bit error counting beyond a capacity of the N-bit counters.

10. The method of claim 9 wherein at least one of the N-bit counters comprise 8-bit counters.