Error correction device and method thereof

• US 7,617,437 B2
• Filed: 02/21/2006
• Issued: 11/10/2009
• Est. Priority Date: 02/21/2006
• Status: Active Grant

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Moyer, William C.
• Primary Examiner(s): Baderman, Scott T
• Assistant Examiner(s): RIZK, SAMIR WADIE
• Application Number:
  US11/359,329
• Publication Number:
  US 20070220354A1
• Time in Patent Office: 1,358 Days
• Field of Search: 714/6, 714/752, 714/758, 714/763
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1052 Bypassing or disabling error detection or correction

Abstract

A device for error correction includes a memory control module to disable error processing for a memory location depending on the state of a status indicator. The status indicator can be set so that error processing is disabled when valid error correction and detection information for the memory location is not available, such as after a reset or power-on event. In addition, the memory control module can promote partial write requests to full write requests when error processing is disabled to ensure that valid error detection and correction data is calculated for the memory location. By disabling error processing until valid error detection and correction information is available, the number of unnecessary or invalid error processing operations is reduced, thereby conserving device resources.

Claims

1. A method:

determining a condition of a first error correction status indicator associated with a first memory location; and

in response to determining that the first error correction status indicator is in a first condition, disabling error processing for a first access request to the first memory location, wherein error processing is selected from a group consisting of error detection and error correction, wherein disabling comprises responding to the first access request without performing error processing.

2. The method of claim 1, further comprising:

in response to determining that the first error correction status indicator is in a second condition, enabling error processing for the first access request to the first memory location.

3. The method of claim 1, wherein the first access request is a partial write operation requesting data of a first size to be written, and further comprising:

promoting the partial write operation to a full write operation in response to determining the first error correction status indicator is in the first condition, the full write operation requesting data of a second size to be written.

4. The method of claim 3, further comprising:

calculating error correction information for the full write operation.

5. The method of claim 3, wherein the second size is a full width of an error correction data unit associated with the first memory location.

6. The method of claim 3, further comprising:

changing the first error correction status indicator to a second condition after promoting the partial write operation.

7. The method of claim 1, wherein the first access request is a partial write operation and further comprising:

in response to determining that the first error correction status indicator is in a second condition;

performing error correction or error detection for the first memory location; and

performing the partial write operation by writing data to a portion of the first memory location.

8. The method of claim 1, further comprising:

receiving a reset indication; and

placing the first error correction status indicator in the first condition responsive to receiving the reset indication.

9. The method of claim 8, wherein the first memory location is incorporated in a device, and wherein the reset indication is received in response to the device transitioning from a low power mode to an active mode.

10. The method of claim 1, further comprising:

receiving a second access request to a second memory location;

determining the status of a second error correction status indicator associated with the second memory location;

in response to determining that the second error correction status indicator is in the first condition, disabling error processing for the second access request to the second memory location.

11. A device, comprising:

a memory including a memory location, the memory location comprising;

a data region, and

an error correction region;

a status indicator associated with the memory location;

an error correction module coupled to the memory, the error correction module to perform error correction associated with the memory location; and

an access control module comprising a first input coupled to the status indicator and an output coupled to the error correction module, the access control module to, in response to the status indicator being in a predetermined condition, disable error processing for the memory location, wherein error processing is selected from a group consisting of error detection and error correction.

12. The device of claim 11, wherein, in response to the status indicator being in the predetermined condition, the access control module promotes a partial write operation associated with the memory location to a full write operation.

13. The device of claim 12, wherein the error correction module calculates error correction data associated with the full write operation.

14. The device of claim 11, wherein the access control module further comprises a second input to receive a reset signal, and wherein the access control module causes the status indicator to be placed into the predetermined condition in response to receiving the reset signal.

15. The device of claim 11, wherein the status indicator is a status flag bit associated with the memory location.

16. A method, comprising:

receiving a partial write operation to a memory location;

determining a status of an error correction status indicator associated with the memory location; and

in response to determining that the error correction status indicator is in a first condition, promoting the partial write operation to a flail write operation.

17. The method of claim 16, further comprising:

disabling at least one of error detection or error correction during processing of the partial write operation.

18. The method of claim 16, further comprising:

receiving a reset indication;

placing the error correction status indicator in the first condition responsive to receiving the reset indication.

19. The method of claim 16, further comprising:

calculating error correction information for the full write operation.

20. The method of claim 16, further comprising:

changing the error correction status indicator to a second condition in addition to promoting the partial write operation.