Method and mechanism for performing latch-up check on an IC design

• US 7,617,465 B1
• Filed: 09/15/2005
• Issued: 11/10/2009
• Est. Priority Date: 09/16/2004
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Cadouri, Eitan
• Primary Examiner(s): Levin; Naum B
• Application Number:
  US11/229,324
• Time in Patent Office: 1,517 Days
• Field of Search: 716 4- 6, 716 8- 11
• US Class Current: 716/106
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Disclosed is a system and method for performing latchup checks for an IC design. In one approach, partitioning is used to create separate sections of the geometry to analyze. The data is then checked by performing graph manipulations.

Claims

1. A method of performing a Design Rule Check of an IC design, comprising:

partitioning a geometry associated with the IC design;

determining distances within various points in the geometry;

creating connectivity graphs by a processor between a source and a destination for the various points in an nwell or pwell structure of the geometry, wherein distances associated with the various points in the nwell or pwell structure are measured by traversing a plurality of different paths between the source and the destination of the connectivity graphs;

storing the connectivity graphs on a volatile or non-volatile computer usable medium device or displaying the connectivity graphs in a display device; and

analyzing the connectivity graphs to determine if a design rule has been violated.

2. The method of claim 1 in which one or more scan lines are created to partition the geometry.

3. The method of claim 2 in which a set of grid points is created along each scan line.

4. The method of claim 3 in which the measured distances comprise distances to/from the grid points.

5. The method of claim 3 in which the connectivity graphs are built to/from the grid points.

6. The method of claim 1 in which paths are identified, wherein distances are analyzed for each of the paths.

7. The method of claim 1 further comprising:

determining whether a parasitic effect exists in the IC design.

8. The method of claim 7 in which the parasitic effect comprises latch-up.

9. The method of claim 1 in which the geometry comprises two shapes within a third shape.

10. The method of claim 1 in which the geometry comprises the nwell or pwell structure.

11. A system for performing a Design Rule Check of an IC design, comprising:

means for partitioning a geometry associated with the IC design;

means for determining distances within various points in the geometry;

a processor for creating connectivity graphs between a source and a destination for the various points in an nwell or pwell structure of the geometry, wherein distances associated with the various points in the nwell or pwell structure are measured by traversing a plurality of different paths between the source and the destination of the connectivity graphs;

a volatile or non-volatile computer usable medium device for storing the connectivity graphs or a display device for displaying the connectivity graphs; and

means for analyzing the connectivity graphs to determine if a design rule has been violated.

12. The system of claim 11 in which one or more scan lines are created to partition the geometry.

13. The system of claim 12 in which a set of grid points is created along each scan line.

14. The system of claim 13 in which the measured distances comprise distances to/from the grid points.

15. The system of claim 13 in which the connectivity graphs are built to/from the grid points.

16. The system of claim 11 in which paths are identified, wherein distances are analyzed for each of the paths.

17. The system of claim 11 further comprising:

means for determining whether a parasitic effect exists in the IC design.

18. The system of claim 17 in which the parasitic effect comprises latch-up.

19. The system of claim 11 in which the geometry comprises two shapes within a third shape.

20. The system of claim 11 in which the geometry comprises the nwell or pwell structure.

21. A computer program product comprising a volatile or non-volatile computer usable storage medium device having executable code to execute by a processor a process for performing a Design Rule Check of an IC design, the process comprising:

partitioning a geometry associated with the IC design;

determining distances within various points in the geometry;

creating connectivity graphs between a source and a destination for the various points in an nwell or a pwell structure of the geometry, wherein distances associated with the various points in the nwell or pwell structure are measured by traversing a plurality of different paths between the source and the destination of the connectivity graphs;

storing the connectivity graphs or displaying the connectivity graphs on a display device; and

analyzing the connectivity graphs to determine if a design rule has been violated.

22. The computer program product of claim 21 in which one or more scan lines are created to partition the geometry.

23. The computer program product of claim 22 in which a set of grid points is created along each scan line.

24. The computer program product of claim 23 in which the measured distances comprise distances to/from the grid points.

25. The computer program product of claim 23 in which the connectivity graphs are built to/from the grid points.

26. The computer program product of claim 21 in which paths are identified, wherein distances are analyzed for each of the paths.

27. The computer program product of claim 21 further comprising:

determining whether a parasitic effect exists in the IC design.

28. The computer program product of claim 27 in which the parasitic effect comprises latch-up.

29. The computer program product of claim 21 in which the geometry comprises two shapes within a third shape.

30. The computer program product of claim 21 in which the geometry comprises the nwell or pwell structure.