Method of making a diode read/write memory cell in a programmed state

• US 7,618,850 B2
• Filed: 03/30/2007
• Issued: 11/17/2009
• Est. Priority Date: 12/19/2002
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Herner, S. Brad, Kumar, Tanmay
• Primary Examiner(s): Richards; N Drew
• Assistant Examiner(s): DIALLO, MAMADOU L
• Application Number:
  US11/693,845
• Publication Number:
  US 20070164309A1
• Time in Patent Office: 963 Days
• Field of Search: 438/131, 438/328, 438/128, 438/130, 365/105, 365/103, 257/E27.02, 257/296, 257/208
• US Class Current: 438/131
• CPC Class Codes: G11C 11/5692 read-only digital stores using storage elements with more than two stable states
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2013/0073 Write using bi-directional cell biasing
• CPC Class Codes: H01L 29/868 PIN diodes
• CPC Class Codes: H10B 63/00 Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

Abstract

A method of making a nonvolatile memory device includes fabricating a diode in a low resistivity, programmed state without an electrical programming step. The memory device includes at least one memory cell. The memory cell is constituted by the diode and electrically conductive electrodes contacting the diode.

Claims

1. A method of making a diode, comprising:

forming a first electrode;

forming a semiconductor region in electrical contact with the first electrode, wherein the semiconductor region comprises a p-n or a p-i-n junction in at least one silicon, germanium or silicon-germanium layer;

forming a titanium layer on the semiconductor region;

forming a titanium nitride layer on the titanium layer;

reacting the titanium layer with the semiconductor region to form a titanium silicide, titanium germanide, or titanium silicide-germanide layer on the semiconductor region;

removing the titanium nitride layer and a remaining portion of the titanium layer after the step of reacting; and

forming a second electrode in electrical contact with the titanium silicide, titanium germanide or titanium silicide-germanide layer;

wherein the titanium silicide, titanium germanide or titanium silicide-germanide layer comprises a C49 phase titanium silicide, a C49 phase titanium germanide or a C49 phase titanium silicide-germanide layer.

2. The method of claim 1, wherein the step of forming the semiconductor region comprises:

depositing a first silicon, germanium or silicon-germanium layer of a first conductivity type over the first electrode;

forming a second intrinsic silicon, germanium or silicon-germanium layer on the first layer; and

implanting dopants of a second conductivity type into the second layer to form a third layer of a second conductivity type opposite to the first conductivity type to form a p-i-n diode.

3. The method of claim 1, wherein:

the least one silicon, germanium or silicon-germanium layer comprises the silicon layer; and

the titanium silicide, titanium germanide or titanium silicide-germanide layer comprises the C49 phase titanium silicide layer.

4. The method of claim 1, wherein:

the least one silicon, germanium or silicon-germanium layer comprises the germanium layer; and

the titanium silicide, titanium germanide or titanium silicide-germanide layer comprises the C49 phase titanium germanide layer.

5. The method of claim 1, wherein:

the least one silicon, germanium or silicon-germanium layer comprises the silicon-germanium layer; and

the titanium silicide, titanium germanide or titanium silicide-germanide layer comprises the C49 phase titanium silicide-germanide layer.

6. The method of claim 1, further comprising patterning the semiconductor region such that the semiconductor region has a substantially cylindrical shape.

7. The method of claim 6, further comprising:

forming an insulating layer over the substantially cylindrical semiconductor region prior to the step of reacting; and

planarizing the insulating layer such that it surrounds the semiconductor region.

8. The method of claim 1, wherein:

the step of forming the semiconductor region comprises forming an amorphous or polycrystalline semiconductor region; and

further comprising crystallizing the semiconductor region to form a low resistivity polycrystalline semiconductor region using the titanium silicide, titanium germanide or titanium silicide-germanide layer as a crystallization template.

9. The method of claim 1, wherein the first electrode, the diode and the second electrode form a complete memory cell of a memory device.

10. The method of claim 9, wherein the diode comprises a p-i-n diode which is fabricated in a stable low resistivity, programmed state corresponding to a first memory state of the memory cell without performing an electrical programming step.

11. The method of claim 9, wherein the diode is fabricated in the low resistivity programmed state by crystallizing an amorphous or polycrystalline semiconductor region.

12. The method of claim 11, wherein the step of crystallizing comprises annealing the diode while using the titanium silicide, titanium germanide or titanium silicide-germanide layer comprising the C49 phase as a crystallization template.

13. The method of claim 10, further comprising:

applying a reverse bias greater than a predetermined critical voltage value to the diode to switch the diode to a stable high resistivity, unprogrammed state corresponding to a second memory state of the memory cell; and

applying a forward bias to the diode to switch the diode to the low resistivity, programmed state.

14. The method of claim 1, further comprising monolithically forming at least one additional device level over the diode.

15. A method of making a nonvolatile memory device comprising at least one memory cell which consists essentially of a diode and electrically conductive electrodes contacting the diode, the method comprising:

fabricating the diode in a stable low resistivity, programmed state corresponding to a first memory state of the memory cell without an electrical programming step,

wherein the step of fabricating the diode in the stable low resistivity, programmed state comprises;

forming a high resistivity amorphous or polycrystalline silicon, germanium or silicon-germanium diode;

forming a C49 phase titanium silicide, C49 phase titanium germanide or C49 phase titanium silicide-germanide layer in contact with the high resistivity diode; and

crystallizing the amorphous or polycrystalline diode to the low resistivity state using the titanium silicide, titanium germanide or titanium silicide-germanide layer as a crystallization template.

16. The method of claim 15, further comprising:

applying a reverse bias greater than a predetermined critical voltage value to the diode to switch the diode to a stable high resistivity, unprogrammed state corresponding to a second memory state of the memory cell; and

applying a forward bias to the diode to switch the diode to the low resistivity, programmed state.

17. The method of claim 15, further comprising monolithically forming at least one additional memory device level over the memory cell.

18. A method of operating a diode memory cell, comprising:

providing the diode which is fabricated in a stable low resistivity, programmed state corresponding to a first memory state of the memory cell without an electrical programming step;

applying a reverse bias greater than a predetermined critical voltage value to the diode to switch the diode to a high resistivity, unprogrammed state corresponding to a second memory state of the memory cell; and

applying a forward bias to the diode to switch the diode to the low resistivity, programmed state;

wherein the step of providing the diode which is fabricated in the stable low resistivity programmed state comprises;

forming a high resistivity amorphous or polycrystalline silicon, germanium or silicon-germanium diode;

forming a C49 phase titanium silicide, C49 phase titanium germanide or C49 phase titanium silicide-germanide layer in contact with the high resistivity diode; and

crystallizing the amorphous or polycrystalline diode to the low resistivity state using the titanium silicide, titanium germanide or titanium silicide-germanide layer as a crystallization template.

19. The method of claim 18, wherein the diode comprises a polycrystalline semiconductor p-i-n diode.

20. The method of claim 18, wherein the memory cell consists essentially of the diode and electrically conductive electrodes contacting the diode.

21. The method of claim 20, further comprising sensing a resistivity state of the diode as a data state of the memory cell.