Process for forming an electronic device including discontinuous storage elements

• US 7,619,275 B2
• Filed: 07/25/2005
• Issued: 11/17/2009
• Est. Priority Date: 07/25/2005
• Status: Expired due to Fees

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Hong, Cheong M., Chindalore, Gowrishankar L., Chang, Ko-Min, Swift, Craig T., Sadd, Michael A.
• Primary Examiner(s): Pizarro; Marcos D.
• Assistant Examiner(s): Montalvo; Eva Yan
• Application Number:
  US11/188,935
• Publication Number:
  US 20070020856A1
• Time in Patent Office: 1,576 Days
• Field of Search: 438/270, 438/212, 438/243, 438/216, 438/261, 438/287, 257/330, 257/332, 257/316, 257/315, 257/324, 257/E29.309, 257/E29.3, 977/707, 977/712
• US Class Current: 257/315
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: H01L 21/7624 using semiconductor on insulator [SOI] technology H01L21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L21/84; silicon on sapphire [SOS] technology H01L21/86
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A process for forming an electronic device can include forming a trench within a substrate, wherein the trench includes a wall and a bottom. The process can also include including forming a portion of discontinuous storage elements that lie within the trench, and forming a first gate electrode within the trench after forming the discontinuous storage elements. At least one discontinuous storage element lies along the wall of the trench at an elevation between an upper surface of the first gate electrode and a primary surface of the substrate. The process can also include forming a second gate electrode overlying the first gate electrode and the primary surface of the substrate.

Claims

1. A process for forming an electronic device, the process comprising:

forming a first trench within a substrate, wherein the first trench includes a wall and a bottom and extends from a primary surface of the substrate;

forming discontinuous storage elements over the primary surface and within the first trench, wherein a first portion of the discontinuous storage elements lies within the first trench;

forming a first gate electrode within the first trench after forming the discontinuous storage elements, wherein;

the first gate electrode has an upper surface that lies below the primary surface of the substrate; and

at least part of the first portion of the discontinuous storage elements lies between the first gate electrode and the wall of the first trench;

forming a second gate electrode that overlies the first gate electrode and the primary surface of the substrate, wherein after forming the second gate electrode, at least a part of the first portion of the discontinuous storage elements lies along the wall of the first trench at an elevation between an upper surface of the first gate electrode and the primary surface of the substrate.

2. The process of claim 1, wherein forming the second gate electrode comprises forming the second gate electrode, such that at least a portion of the second gate electrode extends at least partly into the first trench.

3. The process of claim 1, further comprising forming a third gate electrode within the second trench, wherein:

forming the first trench further comprises forming a second trench that is spaced apart from the first trench, wherein the second trench includes a wall and a bottom and extends from a primary surface of the substrate;

forming the discontinuous storage elements further comprises forming the discontinuous storage elements within the second trench, wherein a second portion of the discontinuous storage elements lies within the second trench;

forming the third gate electrode comprises forming the third gate electrode, such that;

the third gate electrode has an upper surface that lies below the primary surface of the substrate; and

at least a part of the second portion of the discontinuous storage elements lies between the third gate electrode and the wall of the second trench; and

after forming the second gate electrode, at least a part of the second portion of the discontinuous storage elements lies along the wall of the second trench at an elevation between the upper surface of the third gate electrode and the primary surface of the substrate.

4. The process of claim 3, further comprising forming a first doped region and a second doped region along the bottoms of the first and second trenches, respectively.

5. The process of claim 3, further comprising forming a third doped region lying along the primary surface of the substrate between the first and second trenches

6. The process of claim 5, wherein forming the third doped region is performed before forming the second gate electrode.

7. The process of claim 5, wherein forming the third doped region is performed after forming the second gate electrode.

8. The process of claim 3, wherein after forming the second gate electrode:

a first charge storage region includes a first discontinuous storage element, wherein the first discontinuous storage element lies closer to the upper surface of the first gate electrode than the first doped region;

a second charge storage region includes a second discontinuous storage element within the first portion of the discontinuous storage elements, wherein the second discontinuous storage element lies closer to the first doped region than the upper surface of the first gate electrode, and wherein the second charge storage region is spaced apart from the first charge storage region;

a third charge storage region includes a third discontinuous storage element, wherein the third discontinuous storage element lies closer to the upper surface of the third gate electrode than the second doped region; and

a fourth charge storage region includes a fourth discontinuous storage element within the second portion of the discontinuous storage elements, wherein the fourth discontinuous storage element lies closer to the second doped region than the upper surface of the third gate electrode, and wherein the fourth charge storage region is spaced apart from the third charge storage region.

9. The process of claim 3, wherein forming the second gate electrode comprises forming the second gate electrode such that:

the second gate electrode overlies the first and third gate electrodes; and

from a top view, lengths of the first and second trenches axe substantially perpendicular to a length of the second gate electrode.

10. The process of claim 3, further comprising forming a fourth gate electrode, wherein:

forming the second gate electrode comprises forming the second gate electrode that overlies the first gate electrode; and

forming the fourth gate electrode comprises forming the fourth gate electrode, such that the fourth gate electrode overlies the third gate electrode; and

from a top view;

a length of the first trench is substantially parallel to a length of the second gate electrode; and

a length of the second trench is substantially parallel to a length of the fourth gate electrode.

11. The process of claim 1, further comprising:

forming a first dielectric layer lying along the wall and bottom of the first trench, wherein forming the discontinuous storage elements comprises forming the discontinuous storage elements over and separate from the first dielectric layer;

forming a second dielectric layer after forming the discontinuous storage elements; and

forming a third dielectric layer after forming the first gate electrode.

12. The process of claim 11, wherein forming the third dielectric layer comprises forming the third dielectric layer, such that at least one discontinuous storage element within the first portion of discontinuous storage elements lies at an elevation between the primary surface of the substrate and an upper surface of a portion of the third dielectric layer that lies within the first trench.

13. The process of claim 1, wherein forming the first gate electrode comprises:

forming a conductive layer after forming the discontinuous storage elements;

polishing the conductive layer to remove a portion of the conductive layer that overlies the primary surface of the substrate; and

recessing the conductive layer within the first trench to form the first gate electrode.

14. The process of claim 1, wherein forming the first gate electrode comprises:

forming a conductive layer after forming the discontinuous storage elements; and

anisotropically etching the conductive layer to form the first gate electrode, which from a cross-sectional view, has a sidewall spacer shape.

15. The process of claim 1, wherein forming discontinuous storage elements comprises forming silicon nanocrystals or forming metal nanoclusters.

16. A process for forming an electronic device, the process comprising:

forming a first trench and a second trench within a substrate, wherein;

the first trench is spaced apart from the second trench; and

each of the first and second trenches includes a wall and a bottom and extends from a primary surface of the substrate;

forming a first dielectric layer within the first and second trenches;

forming discontinuous storage elements over the primary surface, over and separate from the first dielectric layer, and within the first and second trenches, wherein;

a first portion of the discontinuous storage elements lies within the first trench; and

a second portion of the discontinuous storage elements lies within the second trench;

forming a first conductive layer after forming the discontinuous storage elements;

removing a portion of the first conductive layer that overlies the primary surface of the substrate to form a first gate electrode within the first trench and a second gate electrode within the second trench, wherein;

the first gate electrode has an upper surface that lies below the primary surface of the substrate;

a first discontinuous storage element within the first portion of the discontinuous storage elements lies between the first gate electrode and the wall of the first trench;

the second gate electrode has an upper surface that lies below the primary surface of the substrate; and

a second discontinuous storage element within the second portion of the discontinuous storage elements lies between the second gate electrode and the wall of the first trench;

forming a second dielectric layer over the first and second gate electrodes, wherein the second dielectric layer has a first portion with an upper surface within the first trench and a second portion with an upper surface within the second trench;

forming a second conductive layer after removing the portion of the first conductive layer that overlies the primary surface of the substrate; and

patterning the second conductive layer to form a third gate electrode that overlies the first gate electrode and the primary surface of the substrate, wherein after patterning the second conductive layer;

at least a part of the first portion of the discontinuous storage elements lies along the wall of the first trench at an elevation between the upper surface of the first portion of the second dielectric layer and the primary surface of the substrate; and

at least a part of the second portion of the discontinuous storage elements lies along the wall of the second trench at an elevation between the upper surface of the second portion of the second dielectric layer and the primary surface of the substrate.

17. The process of claim 16, further comprising forming a first doped region and a second doped region along the bottoms of the first and second trenches, respectively.

18. The process of claim 17, further comprising forming a third doped region lying along the primary surface of the substrate between the first and second trenches.

19. The process of claim 16, wherein after patterning the second conductive layer:

a first charge storage region includes the first discontinuous storage element, wherein the first discontinuous storage element lies closer to the upper surface of the first gate electrode than the first doped region;

a second charge storage region includes a third discontinuous storage element within the first portion of the discontinuous storage elements, wherein the third discontinuous storage element lies closer to the first doped region than the upper surface of the first gate electrode, and wherein the second charge storage region is spaced apart from the first charge storage region;

a third charge storage region includes the second discontinuous storage element, wherein the second discontinuous storage element lies closer to the upper surface of the second gate electrode than the second doped region; and

a fourth charge storage region includes a fourth discontinuous storage element within the second portion of the discontinuous storage elements, wherein the fourth discontinuous storage element lies closer to the second doped region than the upper surface of the second gate electrode, and wherein the fourth charge storage region is spaced apart from the third charge storage region.

20. The process of claim 16, wherein forming discontinuous storage elements comprises forming silicon nanocrystals or forming metal nanoclusters.