Carrier structure for semiconductor chip and method for manufacturing the same

• US 7,619,317 B2
• Filed: 11/16/2007
• Issued: 11/17/2009
• Est. Priority Date: 11/17/2006
• Status: Active Grant

• Current Assignee: Phoenix Precision Technology Corporation (Unimicron Technology Corporation)
• Original Assignee: Phoenix Precision Technology Corporation (Unimicron Technology Corporation)
• Inventors: Lien, Chung-Cheng, Chang, Chia-Wei
• Primary Examiner(s): Zarneke, David A
• Assistant Examiner(s): Wagner, Jenny L
• Application Number:
  US11/984,349
• Publication Number:
  US 20080116562A1
• Time in Patent Office: 732 Days
• Field of Search: 257/700, 257/787, 257/E23.004, 361760-764, 361767-768, 361/776, 361/783, 174260-262, 425/127
• US Class Current: 257/787
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2924/01012 Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/1815 Shape
• CPC Class Codes: H01L 2924/18162 of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/3511 Warping

Abstract

A carrier structure for a semiconductor chip and a method for manufacturing the same are disclosed. The method includes the following steps: providing a carrier board having at least one through cavity, wherein a removable film is formed on the surface of the carrier board, and a semiconductor chip is temporarily fixed in the through cavity by the removable film; filling the gap between the through cavity of the carrier board and the semiconductor chip with an adhesive material in order to fix the semiconductor chip; and removing the removable film. The disclosed method can reduce the alignment error resulted from the tiny shift of the semiconductor chip caused by jitters before the semiconductor is fixed in the cavity, thereby to increase the accuracy of the alignment, to facilitate fine wiring, and to meet the trend toward compact size of semiconductor packages.

Claims

1. A carrier structure for a semiconductor chip comprising:

a carrier board having at least one through cavity in which a semiconductor chip, having an active surface with a plurality of electrode pads thereon and an opposite inactive surface, is disposed;

an adhesive material filling the gap between the through cavity of the carrier board and the semiconductor chip in order to fix the semiconductor chip, wherein a revealed surface of the adhesive material is a concave surface; and

a built-up structure having at least one dielectric layer, wherein the dielectric layer is formed on the active surface of the semiconductor chip, on one surface of the carrier board on the same side with the active surface of the semiconductor chip, and on the concave surface of the adhesive material so that the combination of the dielectric layer and the concave surfaces of the adhesive material is advantageous to disperse the stress between different materials.

2. The carrier structure as claimed in claim 1, wherein the carrier board comprises a first core layer, a second core layer, and an inner adhesive layer, therewith the inner adhesive layer disposed between the first and second core layers, the first and second core layers made of metals, ceramics, circuit boards, or other dielectric materials, and the inner adhesive layer made of organic dielectric materials, liquid organic resin materials, or pre-preg materials.

3. The carrier structure as claimed in claim 1, wherein the adhesive material is made of organic dielectric materials, liquid organic resin materials, or pre-preg materials.

4. The carrier structure as claimed in claim 1, wherein the active surface of the semiconductor chip has a height the same as, lower than, or higher than that of the surface of the carrier board.

5. The carrier structure as claimed in claim 1, wherein the built-up structure further comprises one circuit layer stacked on every dielectric layer, a plurality of conductive vias, and a plurality of conductive pads, and parts of the conductive vias electrically connect to the conductive pads of the semiconductor chip.

6. A carrier structure for a semiconductor chip comprising:

a carrier board having at least one through cavity in which a semiconductor chip, having an active surface with a plurality of electrode pads thereon and an opposite inactive surface, is disposed;

an adhesive material filling the gap between the through cavity of the carrier board and the semiconductor chip in order to fix the semiconductor chip, the adhesive material having a concave surface where exposed; and

a built-up structure having at least one dielectric layer, wherein the dielectric layer is formed on the active surface of the semiconductor chip, on one surface of the carrier board on the same side with the active surface of the semiconductor chip, and on the concave surface of the adhesive material so that the combination of the dielectric layer and the concave surfaces of the adhesive material is advantageous to disperse the stress between different materials.