Methods of enabling the use of a defective programmable device

• US 7,619,438 B1
• Filed: 10/11/2007
• Issued: 11/17/2009
• Est. Priority Date: 10/11/2007
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Trimberger, Stephen M.
• Primary Examiner(s): Barnie; Rexford N
• Assistant Examiner(s): Hammond; Crystal L
• Application Number:
  US11/974,354
• Time in Patent Office: 768 Days
• Field of Search: 326/9, 326 38- 41, 365/189.12, 365/200, 365/189.01, 714/710, 714/725, 324/528
• US Class Current: 326/10
• CPC Class Codes: G01R 31/318516 Test of programmable logic devices [PLDs]
• CPC Class Codes: H03K 19/17764 for reliability

Abstract

Methods of enabling the use of defective programmable devices. The method comprises performing functional testing for each programmable device of a plurality of programmable devices; identifying each programmable device of the plurality of programmable devices having a defective portion of programmable blocks; identifying, for each programmable device which is identified to have a defective portion of programmable blocks, a location of the defective portion; and storing, for each programmable device which is identified to have a defective portion of programmable blocks, the location of the defective portion on the programmable device.

Claims

1. A method of enabling the use of defective programmable devices, the method comprising:

performing functional testing for each programmable device of a plurality of programmable devices;

identifying each programmable device of the plurality of programmable devices which has a defective portion of programmable blocks;

identifying, for each programmable device which is identified to have a defective portion of programmable blocks, a location of the defective portion of programmable blocks;

storing, for each programmable device which is identified to have a defective portion of programmable blocks, the location of the defective portion of programmable blocks; and

selecting a configuration bitstream for one of the programmable devices, wherein the selected configuration bitstream is selected from a plurality of configuration bitstreams based upon the stored location of the defective portion for the one of the programmable devices.

2. The method of claim 1, further comprising dividing the programmable blocks of the plurality of programmable devices into regions.

3. The method of claim 2, wherein identifying the location of the defective portion of programmable blocks comprises designating a region having the defective portion.

4. The method of claim 3, further comprising categorizing programmable devices having defective portions of programmable blocks in different regions in a common category of defective products.

5. The method of claim 1, wherein storing the location of the defective portion of programmable blocks comprises storing the location in a non-volatile memory of the programmable device.

6. The method of claim 1, further comprising, for each programmable device, programming the programmable device with the selected configuration bitstream.

7. The method of claim 6, further comprising testing the programmed programmable devices.

8. A method of enabling the use of defective programmable devices, the method comprising:

receiving a plurality of programmable devices, each programmable device having an indication of a location of a defective portion of programmable blocks;

selecting, for each programmable device, a configuration bitstream of a plurality of configuration bitstreams implementing a same circuit design, wherein the selection of a configuration bitstream is based upon the location of the defective portion of programmable blocks; and

programming each programmable device with a corresponding selected configuration bitstream of the plurality of configuration bitstreams.

9. The method of claim 8, further comprising receiving, for each programmable device, the indication of the location of the defective portion of programmable blocks.

10. The method of claim 8, wherein receiving the plurality of programmable devices comprises receiving a plurality of programmable devices each having an indication of the location of the defective portion of programmable blocks which is readable on the device.

11. The method of claim 8, wherein receiving the plurality of programmable devices comprises receiving a plurality of programmable devices each having a non-volatile memory storing the location of the defective portion of programmable blocks.

12. The method of claim 8, wherein selecting the configuration bitstream comprises selecting the configuration bitstream based upon the location of the defective portion of programmable blocks being in a predetermined region of the programmable blocks.

13. The method of claim 12, wherein selecting the configuration bitstream comprises selecting the configuration bitstream associated with the predetermined region.

14. The method of claim 8, further comprising testing, for each programmable device, the programmable device programmed with the corresponding selected configuration bitstream.

15. A device having programmable circuits, the device comprising:

a plurality of programmable circuits, wherein at least a portion of the programmable circuits is defective;

a non-volatile memory storing an indication of a location of the portion of the programmable circuits which is defective; and

a plurality of configuration memory elements storing configuration bits of a selected configuration bitstream, wherein the selected configuration bitstream is selected from a plurality of configuration bitstreams based upon the indication stored in the non-volatile memory.

16. The device of claim 15, wherein the plurality of programmable circuits comprises configurable blocks.

17. The device of claim 15, wherein the plurality of programmable circuits comprises blocks of random access memory.

18. The device of claim 15, further comprising an input/output block for outputting the indication of the location of the portion of the programmable circuits which is defective.

19. The device of claim 18, further comprising configuration logic coupled to the non-volatile memory to provide the indication of the location of the portion of the programmable circuits which is defective by way of the input/output block.

20. The device of claim 18, further comprising a configuration controller coupled to the non-volatile memory to provide the indication of the location of the portion of the programmable circuits which is defective by way of the input/output block.