GPS processing arrangement

• US 7,619,560 B2
• Filed: 06/07/2006
• Issued: 11/17/2009
• Est. Priority Date: 06/08/2005
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Penna, David E., Tickell, Stephen A.
• Primary Examiner(s): Tarcza, Thomas H
• Assistant Examiner(s): Mull, Fred H
• Application Number:
  US11/916,345
• Publication Number:
  US 20090073037A1
• Time in Patent Office: 1,259 Days
• Field of Search: 342/357.12, 342/357.03
• US Class Current: 342/357.77
• CPC Class Codes: G01S 19/24 Acquisition or tracking or demodulation of signals transmitted by the system synchronisation aspects of direct sequence spread spectrum modulation H04B1/7073
• CPC Class Codes: G01S 19/34 Power consumption
• CPC Class Codes: G01S 19/37 Hardware or software details of the signal processing chain

Abstract

A software GPS processing arrangement comprising a FIFO buffer for receiving a stream of the GPS signal samples, a memory, a DMA controller for transferring the GPS signal samples from the FIFO buffer to the memory, a CPU running GPS signal processing software configured to retrieve the GPS signal samples from the memory and process them to obtain a position fix, and a counter operating independently of the DMA controller and the CPU for keeping count of the number of streamed GPS signal samples.

Claims

1. A software GPS processing arrangement comprising

a FIFO buffer for receiving a stream of the GPS signal samples;

a memory;

a DMA controller for transferring the GPS signal samples from the FIFO buffer to the memory;

a CPU configured for running GPS signal processing software configured to retrieve the GPS signal samples from the memory and process them to obtain a position fix; and

a counter configured for operating independently of the DMA controller and the CPU and for keeping count of the number of streamed GPS signal samples by incrementing a count in response to a frame signal indicating a word boundary in the stream of GPS signal samples.

2. An arrangement according to claim 1 wherein the counter is configured for receiving an external count signal in which each individual count indicates the streaming of two or more GPS signal samples.

3. The arrangement of claim 1, further including another counter that is incremented for each GPS signal sample sent to the FIFO buffer.

4. The arrangement of claim 1, further including

a serial-to-parallel port for serially receiving the GPS signal samples, storing the received GPS signals under the control of a received clock signal and providing and outputting multiple ones of the received GPS signal samples in parallel according to word boundaries;

another counter for incrementing a count for each clock cycle of a clock and outputting a frame signal representing a word boundary; and

wherein the counter operating independently of the DMA controller is incremented in response to the outputted frame signal from the other counter.

5. The arrangement of claim 4 wherein the other counter generates a carry-out signal every 16 bits that is used as the frame signal, the serial-to-parallel port outputs 16 bits of GPS signal samples in parallel and the counter operating independently of the DMA controller is integrated with the CPU.

6. The arrangement of claim 4, wherein CPU is further configured for calculating the sample time by subtracting the number of GPS signal samples in the FIFO buffer, representing in words, and the DMA target address, modified by an offset from the start of a DMA memory buffer, from the count of the counter operating independently of the DMA controller.

7. The arrangement of claim 1, wherein the CPU is further configured to determine a sample time for a set of GPS signal samples transferred to the memory by

monitoring a DMA target address to detect a DMA idle phase;

reading, in response to detecting a DMA idle phase, a register that indicates receipt of GPS signal samples in the FIFO buffer;

reading, in response to an indication of receipt of GPS signal samples in the FIFO buffer, the count of the counter operating independently of the DMA controller; and

calculating the sample time as a function of the DMA target address, the count of the counter operating independently of the DMA controller and the number of GPS signal samples in the FIFO buffer.

8. The arrangement of claim 1, wherein the CPU is further configured to operate at different clock speeds and wherein during a transition between different clock speeds transfers using the DMA controller are interrupted.

9. The arrangement of claim 8, wherein the counter generating the frame signal continues to increment while the DMA controller is interrupted.