Apparatus, method, and system for flash memory
First Claim
1. An apparatus comprising:
- a plurality of multiple level memory cells, each of the plurality of multiple level memory cells coupled to one of a plurality of wordlines and each of the plurality of multiple level memory cells including a plurality of logical memory pages; and
a control circuit coupled to the plurality of wordlines, the control circuit operable to progressively program each of the plurality of multiple level memory cells in at least one sequence including separation of the programming of a first logical memory page and a second logical memory page in any one of the plurality of multiple level memory cells by at least N−
1 programming operations to memory cells either coupled to a different wordline or included in a different logical even page or a different logical odd page from the any one of the plurality of multiple level memory cell that includes the first logical memory page and the second logical memory page, wherein N is an integer equal to the number of data bits the plurality of multiple level memory cells are operable to store.
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Accused Products
Abstract
Methods, apparatus, systems, and data structures are disclosed, including a plurality of multiple level memory cells, each of the plurality of multiple level memory cells coupled to one of a plurality of wordlines and each of the plurality of multiple level memory cells including a plurality of logical memory pages; a control circuit coupled to the plurality of wordlines, the control circuit operable to progressively program each of the plurality of multiple level memory cells in at least one sequence including separation of the programming of a first logical memory page and a second logical memory page in any one of the plurality of multiple level memory cells by at least N−1 programming operations to memory cells either coupled to a different wordline or included in a different logical even page or a different logical odd page.
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Citations
29 Claims
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1. An apparatus comprising:
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a plurality of multiple level memory cells, each of the plurality of multiple level memory cells coupled to one of a plurality of wordlines and each of the plurality of multiple level memory cells including a plurality of logical memory pages; and a control circuit coupled to the plurality of wordlines, the control circuit operable to progressively program each of the plurality of multiple level memory cells in at least one sequence including separation of the programming of a first logical memory page and a second logical memory page in any one of the plurality of multiple level memory cells by at least N−
1 programming operations to memory cells either coupled to a different wordline or included in a different logical even page or a different logical odd page from the any one of the plurality of multiple level memory cell that includes the first logical memory page and the second logical memory page, wherein N is an integer equal to the number of data bits the plurality of multiple level memory cells are operable to store. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method comprising:
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programming a first logical memory page of a first multiple level memory cell; and programming at least N−
1 other logical memory pages in one or more other multiple level memory cells in a same memory block as the first multiple level memory cell before programming a second logical memory page of the first multiple level memory cell, wherein N is an integer equal to the number of data bits the first multiple level memory cell is operable to store. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17)
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18. A method comprising:
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programming a plurality of multiple level memory cells, including, programming each of a plurality of logical memory pages included in each of the plurality of multiple level memory cells progressively using a plurality of programming processes, and applying erase compaction to at least one of the plurality of programming processes. - View Dependent Claims (19, 20, 21)
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22. A machine-readable medium having instructions stored thereon that, when executed by a machine, cause the machine to perform:
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programming a first logical memory page of a first multiple level memory cell; and programming at least N−
1 other logical memory pages in one or more other multiple level memory cells in a same memory block as the first multiple level memory cell before programming a second logical memory page of the first multiple level memory cell, wherein N is an integer equal to the number of data bits the first multiple level memory cell is operable to store. - View Dependent Claims (23)
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24. An apparatus comprising:
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a plurality of multiple level memory cells, each of the plurality of multiple level memory cells coupled to one of a plurality of wordlines and included in either a logical even page or a logical odd page coupled to each one of the plurality of wordlines, each of the plurality of multiple level memory cells including N logical memory pages, wherein N is an integer equal to the number of data bits each of the plurality of multiple level memory cells is operable to store; and at least one of the plurality of multiple level memory cells including a programmed memory cell having all of the N logical memory pages included in the programmed memory cell programmed with a data bit, the programmed memory cell coupled to a first wordline of the plurality of wordlines and the programmed memory cell included in either the logical even page or the logical odd page coupled to the first wordline; wherein any of the plurality of multiple level memory cells either coupled to a wordline adjacent to the first wordline or coupled to the first wordline and on a different logical even page or a different logical odd page from the programmed memory cell have at least N−
1 logical memory pages programmed with a data bit, and at least one of the any of the plurality of multiple level memory cell has no more than N−
1 logical memory pages programmed. - View Dependent Claims (25, 26)
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27. A system comprising:
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a processor coupled to a plurality of multiple level memory cells, each of the plurality of multiple level memory cells coupled to one of a plurality of wordlines and each of the plurality of multiple level memory cells including a plurality of logical memory pages; and a control circuit coupled to the plurality of wordlines, the control circuit operable to progressively program each of the plurality of multiple level memory cells in at least one sequence including separation of the programming of a first logical memory page and a second logical memory page in any one of the plurality of multiple level memory cells by at least N−
1 programming operations to memory cells either coupled to a different wordline or included in a different logical even page or a different logical odd page from the any one of the plurality of multiple level memory cell that includes the first logical memory page and the second logical memory page, wherein N is an integer equal to the number of data bits the plurality of multiple level memory cells are operable to store. - View Dependent Claims (28, 29)
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Specification