Apparatus, method, and system for flash memory

• US 7,619,918 B2
• Filed: 12/29/2006
• Issued: 11/17/2009
• Est. Priority Date: 12/29/2006
• Status: Active Grant

• Current Assignee: Intel NDTM US LLC (Intel Corporation)
• Original Assignee: Intel Corporation
• Inventors: Aritome, Seiichi
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US11/618,661
• Publication Number:
  US 20080158950A1
• Time in Patent Office: 1,054 Days
• Field of Search: 365/185.03, 365/185.24
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits

Abstract

Methods, apparatus, systems, and data structures are disclosed, including a plurality of multiple level memory cells, each of the plurality of multiple level memory cells coupled to one of a plurality of wordlines and each of the plurality of multiple level memory cells including a plurality of logical memory pages; a control circuit coupled to the plurality of wordlines, the control circuit operable to progressively program each of the plurality of multiple level memory cells in at least one sequence including separation of the programming of a first logical memory page and a second logical memory page in any one of the plurality of multiple level memory cells by at least N−1 programming operations to memory cells either coupled to a different wordline or included in a different logical even page or a different logical odd page.

Claims

1. An apparatus comprising:

a plurality of multiple level memory cells, each of the plurality of multiple level memory cells coupled to one of a plurality of wordlines and each of the plurality of multiple level memory cells including a plurality of logical memory pages; and

a control circuit coupled to the plurality of wordlines, the control circuit operable to progressively program each of the plurality of multiple level memory cells in at least one sequence including separation of the programming of a first logical memory page and a second logical memory page in any one of the plurality of multiple level memory cells by at least N−

1 programming operations to memory cells either coupled to a different wordline or included in a different logical even page or a different logical odd page from the any one of the plurality of multiple level memory cell that includes the first logical memory page and the second logical memory page, wherein N is an integer equal to the number of data bits the plurality of multiple level memory cells are operable to store.

2. The apparatus of claim 1, further including a first plurality of bitlines coupled to the control circuit and to a first group of the plurality of multiple level memory cells in a logical even page, and a second plurality of bitlines coupled to the control circuit and to a second plurality of the multiple level memory cells in a second logical page.

3. The apparatus of claim 1, wherein the plurality of multiple level memory cells includes at least one NAND flash memory cell.

4. The apparatus of claim 1, wherein at least one of the plurality of multiple level memory cells includes at least one memory cell operable to store at least four bits of data.

5. The apparatus of claim 1, wherein a first portion of the plurality of multiple level memory cells coupled to a same wordline are included in a first logical page, and a second portion of the multiple level memory cells coupled to the same wordline are included in a second logical page.

6. The apparatus of claim 1, further including the control circuit including stored instructions including a sequence of logical page numbers for programming at least a portion of the plurality of multiple level memory cells.

7. The apparatus of claim 1, wherein at least one of the plurality of multiple level memory cells includes having a threshold voltage within one of at least sixteen designated threshold voltage distributions.

8. The apparatus of claim 1, wherein at least one of the plurality of multiple level memory cells includes having a threshold voltage within a lowest positive threshold voltage distribution of a plurality of designated threshold voltage distributions, the lowest positive threshold voltage distribution including a wider range of threshold voltages than any other of the plurality of designated threshold voltages that include positive threshold voltages.

9. A method comprising:

programming a first logical memory page of a first multiple level memory cell; and

programming at least N−

1 other logical memory pages in one or more other multiple level memory cells in a same memory block as the first multiple level memory cell before programming a second logical memory page of the first multiple level memory cell, wherein N is an integer equal to the number of data bits the first multiple level memory cell is operable to store.

10. The method of claim 9, wherein the first logical memory page is one of a first lower page, a second lower page, and a third lower page of the first multiple level memory cell.

11. The method of claim 9, wherein the second logical memory page of the first multiple level memory cell is the second lower page, if the first logical memory page is the first lower page of the first multiple level memory cell.

12. The method of claim 9, wherein the second logical memory page of the first multiple level memory cell is an UPPER page, if the first logical memory page is the third lower page of the first multiple level memory cell.

13. The method of claim 9, wherein programming the at least N−

1 other logical memory pages includes programming as a first of the at least N−

1 other logical memory pages a first logical memory page of a second multiple level memory cell of the one or more other multiple level memory cells, wherein the second multiple level memory cell is coupled to a same wordline as the first multiple level memory cell, and is in a different logical page than a logical page that includes the first multiple level memory cell.

14. The method of claim 9, wherein programming the at least three other physical pages includes programming as a second of the at least three other physical pages a first physical page of a third multiple level memory cell of the one or more other multiple level memory cells, wherein the third multiple level memory cell is coupled to a different wordline from the same wordline coupled to the first multiple level memory cell, and is in the logical page that includes the first multiple level memory cell.

15. The method of claim 14, wherein the different wordline is a next adjacent wordline in the same memory block.

16. The method of claim 9, wherein programming the at least three other physical pages includes programming as a third of the at least three other physical pages a second physical page of the second multiple level memory cell of the one or more other multiple level memory cells, wherein the second multiple level memory cell is coupled to a different wordline from the same wordline that includes the first multiple level memory cell, and is in a different logical page from the logical page that includes the first multiple level memory cell.

17. The method of claim 9, wherein programming at least N−

1 other physical pages includes programming N−

1 other physical pages and then programming the second physical page of the first multiple level memory cell.

18. A method comprising:

programming a plurality of multiple level memory cells, including,

programming each of a plurality of logical memory pages included in each of the plurality of multiple level memory cells progressively using a plurality of programming processes, and

applying erase compaction to at least one of the plurality of programming processes.

19. The method of claim 18, wherein applying erase compaction includes after the programming of a logical memory page in at least one of the plurality of logical memory pages in a first one of the plurality of memory cells, designating a second range of threshold voltages as the range of threshold voltages included in a threshold voltage distribution associated with an erased memory cell, wherein the second range of threshold voltages includes a second range of threshold voltages that is smaller than a fist range of threshold voltages designated as a first range of threshold voltages included in a first threshold voltage distribution associated with the erased memory cell before the programming of the logical memory page.

20. The method of claim 18, wherein applying erase compaction includes after the programming of the logical memory page in at least one of the plurality of logical memory pages in the first one of the plurality of memory cells, performing a compaction verification operation.

21. The method of claim 20, wherein performing a compaction verification operation includes measuring a current for at least one of a series string including at least one of the memory cells programmed.

22. A machine-readable medium having instructions stored thereon that, when executed by a machine, cause the machine to perform:

programming a first logical memory page of a first multiple level memory cell; and

programming at least N−

1 other logical memory pages in one or more other multiple level memory cells in a same memory block as the first multiple level memory cell before programming a second logical memory page of the first multiple level memory cell, wherein N is an integer equal to the number of data bits the first multiple level memory cell is operable to store.

23. The machine-readable medium of claim 22, wherein programming a first logical memory page includes programming a third lower page LP-3 of the first multiple level memory cell.

24. An apparatus comprising:

a plurality of multiple level memory cells, each of the plurality of multiple level memory cells coupled to one of a plurality of wordlines and included in either a logical even page or a logical odd page coupled to each one of the plurality of wordlines, each of the plurality of multiple level memory cells including N logical memory pages, wherein N is an integer equal to the number of data bits each of the plurality of multiple level memory cells is operable to store; and

at least one of the plurality of multiple level memory cells including a programmed memory cell having all of the N logical memory pages included in the programmed memory cell programmed with a data bit, the programmed memory cell coupled to a first wordline of the plurality of wordlines and the programmed memory cell included in either the logical even page or the logical odd page coupled to the first wordline;

wherein any of the plurality of multiple level memory cells either coupled to a wordline adjacent to the first wordline or coupled to the first wordline and on a different logical even page or a different logical odd page from the programmed memory cell have at least N−

1 logical memory pages programmed with a data bit, and at least one of the any of the plurality of multiple level memory cell has no more than N−

1 logical memory pages programmed.

25. The apparatus of claim 24, wherein at least one of the any of the plurality of multiple level memory cells has no more than N−

1 logical memory pages programmed when all of the plurality of multiple level memory cells either coupled to a wordline adjacent to the first wordline or coupled to the first wordline and included in a different logical even page or a different logical odd page from the programmed memory cell have at least N−

1 logical memory pages programmed with data bits.

26. The apparatus of claim 24, wherein each of the plurality of multiple level memory cells includes 4 logical memory pages.

27. A system comprising:

a processor coupled to a plurality of multiple level memory cells, each of the plurality of multiple level memory cells coupled to one of a plurality of wordlines and each of the plurality of multiple level memory cells including a plurality of logical memory pages; and

a control circuit coupled to the plurality of wordlines, the control circuit operable to progressively program each of the plurality of multiple level memory cells in at least one sequence including separation of the programming of a first logical memory page and a second logical memory page in any one of the plurality of multiple level memory cells by at least N−

1 programming operations to memory cells either coupled to a different wordline or included in a different logical even page or a different logical odd page from the any one of the plurality of multiple level memory cell that includes the first logical memory page and the second logical memory page, wherein N is an integer equal to the number of data bits the plurality of multiple level memory cells are operable to store.

28. The system of claim 27, wherein the processor further includes stored instructions operable for programming the plurality of multiple level memory cells.

29. The system of claim 27, wherein the processor coupled to the plurality of multiple level memory cells further includes a digital camera.