Hardware assisted non-volatile memory-to-input/output direct memory access (DMA) transfer

• US 7,620,748 B1
• Filed: 04/06/2006
• Issued: 11/17/2009
• Est. Priority Date: 04/06/2006
• Status: Active Grant

• Current Assignee: BiTMICRO, LLC (BiTMICRO Networks, Inc.)
• Original Assignee: BiTMICRO Networks, Inc.
• Inventors: Bruce, Rey, Bruce, Ricardo, Zalzos Sambilay, Jr., Federico, Leung Chiw, Bernard Sherwin
• Primary Examiner(s): Tsai, Henry W. H.
• Assistant Examiner(s): Nam, Hyun
• Application Number:
  US11/399,736
• Time in Patent Office: 1,321 Days
• Field of Search: 710/22, 710/308
• US Class Current: 710/22
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

In conventional storage device system, data transfer from memory to IO bus has to go through an intermediate volatile memory (cache). Data transfer therefore is completed in two steps—data is transferred from memory to cache and then from cache to the IO bus. Memory-to-cache transfer is handled by one DMA engine and another DMA engine for cache-to-IO transfer. To start the transfer, processor prepares the DMA transfer from memory to cache. Upon completion of the memory-to-cache transfer, the processor is interrupted to prepare the transfer from cache to IO. In between transfers, the processor has to intervene to setup the next transfer utilizing the precious processor cycles. The present invention improves on the above process using two novel schemes; 1) The use of dependency table to facilitate the transfer from memory-to-IO with less intervention from the processor and 2) the use of Bus Snooping scheme to bypass the transfer to cache making the transfer directly from memory to IO bus. This makes the transfer from memory to IO completed in single transfer.

Claims

1. A data transfer method comprising the steps of:

checking a data structure for an entry comprising a state set to be free;

assigning an index of the entry to a first data descriptor and a second data descriptor whereby a data buffer is accessed by a first and second DMA engine according to the first and second data descriptor for dual channel DMA data transfer without CPU intervention subsequent to the first and second data descriptor being prepared by CPU;

assigning a value to a threshold of the entry;

setting the state to be ready upon assigning the threshold;

preparing the first data descriptor and the second data descriptor by one or more CPU;

transferring data from a source device to a data buffer using a first DMA engine according to the first data descriptor subsequent to the preparation completion thereof;

setting the state to be active upon the first DMA engine starting data transfer;

setting the state to be completed upon the first DMA engine data transfer reaching the threshold of the entry;

transferring data from the data buffer to a destination device using a second DMA engine according to the second data descriptor upon the preparation completion thereof and the state being assigned to be completed; and

setting the state to be free subsequent to the second DMA engine starting data transfer.

2. A data transfer method comprising the steps of:

checking a data structure for an entry comprising a state set to be free;

assigning an index of the entry to a first data descriptor and a second data descriptor whereby a data buffer is accessed by a first and second DMA engine according to the first and second data descriptor for dual channel DMA data transfer without CPU intervention subsequent to the first and second data descriptor being prepared by CPU;

assigning a value to a threshold of the entry;

setting the state to be ready upon assigning the threshold;

preparing the first data descriptor and the second data descriptor by one or more CPU;

transferring data from a source device to a data buffer using a first DMA engine according to the first data descriptor subsequent to the preparation completion thereof;

setting the state to be active upon the first DMA engine starting data transfer;

setting the state to be completed upon the first DMA engine data transfer reaching the threshold of the entry;

transferring data from the data buffer to a destination device using a second DMA engine according to the second data descriptor upon the preparation completion thereof and the state being assigned to be completed;

setting the state to be initiated upon the second DMA engine starting data transfer; and

setting the state to be free upon the first DMA engine detecting the status being set to initiated.

3. The method of claim 2 wherein the second DMA engine is flow controlled for preventing a buffer overflow of the second DMA engine.

4. A data transfer method comprising the steps of:

checking a data structure for an entry comprising a state set to be free;

assigning an index of the entry to a first data descriptor and a second data descriptor;

assigning a value to a threshold of the entry;

setting the state to be ready upon assigning the threshold;

preparing the first data descriptor and the second data descriptor by one or more CPU;

transferring data from a source device to a data buffer using a first DMA engine according to the first data descriptor subsequent to the preparation completion thereof;

monitoring an address bus for detecting a starting address of the first data descriptor;

monitoring a data bus for detecting a first valid data of the first DMA engine;

transferring one or more valid data of the first DMA engine to a destination device using a second DMA engine according to the second data descriptor upon detecting the first valid data of the first DMA engine;

setting the state to be completed upon the first DMA engine data transfer reaching the threshold of the entry;

setting the state to be initiated subsequent to the second DMA engine starting data transfer and the state being set to completed; and

setting the state to be free upon the first DMA engine detecting the status being set to initiated.

5. The method of claim 4, after the step of transferring one or more valid data of the first DMA engine, further comprising the steps of:

Stopping the second DMA engine data transfer upon a buffer overflow; and

transferring one or more data from the data buffer to the destination device using a second DMA engine according to the second data descriptor upon the first DMA engine data transfer reaching the threshold of the entry.

6. A data transfer method comprising the steps of:

checking a data structure for an entry comprising a state set to be free;

assigning an index of the entry to a first data descriptor and a second data descriptor;

assigning a value to a threshold of the entry;

setting the state to be ready upon assigning the threshold;

preparing the first data descriptor and the second data descriptor by one or more CPU;

transferring data from a source device to a data buffer using a first DMA engine according to the first data descriptor subsequent to the preparation completion thereof;

monitoring an address bus for detecting a starting address of the first data descriptor;

monitoring a data bus for detecting a first valid data of the first DMA engine;

transferring one or more valid data of the first DMA engine to a destination device using a second DMA engine according to the second data descriptor upon detecting the first valid data of the first DMA engine;

setting the state to be completed upon the first DMA engine data transfer reaching the threshold of the entry; and

setting the state to be free subsequent to the second DMA engine starting data transfer and the state being set to completed.

7. A data structure stored in a computer-readable storage medium, said data structure for use with a storage device disposed to coordinate dual channel DMA transfers by at least using said data structure, a first DMA engine, a second DMA engine, and a data buffer;

said data structure comprising;

one or more entries, including a first entry that comprises a status initialized to be free and a first index field;

wherein a first data descriptor and a second data descriptor are assigned to the first entry if the status is free;

wherein the first and second DMA engines are disposed to respectively perform said DMA transfers by accessing the data buffer as specified by the first and second data descriptors;

wherein the first entry is further associated with a first threshold field;

wherein the status of the first entry is updated to indicate that values have been assigned respectively to the first index field and the first threshold field;

wherein the first data descriptor and the second data descriptor are prepared by one or more CPU;

wherein the first DMA engine transfers data from a source device to the data buffer according to the first data descriptor subsequent to the preparation completion thereof;

wherein the status is set to be active upon the first DMA engine starting data transfer;

wherein the status is set to be completed upon the first DMA engine data transfer reaching the threshold;

wherein the second DMA engine transfers data from the data buffer to a destination device according to the second data descriptor upon the preparation completion thereof and the status being set to be completed;

wherein the status is set to be initiated upon the second DMA engine starting data transfer; and

wherein the status is set to be free upon the first DMA engine detecting the status being set to initiated.

8. The data structure of claim 7 wherein:

the data buffer includes a data stripe buffer, said data stripe buffer including a data stripe buffer size; and

at one of the entries further includes a range field for tracking an end address of the data stripe buffer and a number of times a data stripe of data is transferred from the data stripe buffer.

9. The data structure of claim 7 wherein the first data descriptor and the second data descriptor are prepared concurrently.

10. The data structure of claim 7 wherein the first and second DMA engine transfer data from the source device to the destination device in response to the data structure without intervention from the one or more CPU subsequent to the first and second data descriptors preparation completion thereof.

11. The data structure of claim 7:

wherein the data buffer comprises one or more data stripe buffer;

wherein one or more entry further comprises one or more range for tracking end address of the one or more data stripe buffer and number of data stripe fully transferred.

12. The data structure of claim 11 wherein the one or more range further comprises one or more offset select, one or more minimum range and one or more maximum range whereby size of the one or more data stripe buffer is determined and compare logic for generating completed status is reduced.

13. The data structure of claim 11 wherein data transfer to the one or more stripe is handled by one or more DMA engine.