Mapping memory in a parallel processing environment

• US 7,620,791 B1
• Filed: 04/14/2006
• Issued: 11/17/2009
• Est. Priority Date: 04/14/2006
• Status: Active Grant

• Current Assignee: Mellanox Technologies Limited (NVIDIA Corporation)
• Original Assignee: Tilera Corporation (NVIDIA Corporation)
• Inventors: Agarwal, Anant, Wentzlaff, David, Mattina, Matthew
• Primary Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US11/404,207
• Time in Patent Office: 1,313 Days
• Field of Search: 711/100, 711/154, 711/156, 711/202, 711/203
• US Class Current: 711/202
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0844 Multiple simultaneous or quasi-simultaneous cache accessing
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]

Abstract

An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles. The integrated circuit further includes a plurality of memory interface modules including circuitry to access a respective external memory, each memory interface module coupled to a switch of at least one tile. At least some of the tiles are configured to access an address in an external memory by sending from the switch a packet that includes a physical memory address that includes the external memory address and information identifying the corresponding external memory.

Claims

1. An integrated circuit, comprising:

a plurality of tiles, each tile comprising

a processor, and

a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles; and

a plurality of memory interface modules including circuitry to access a respective external memory, each memory interface module coupled to a switch of at least one tile;

wherein at least some of the tiles are configured to access an address in an external memory by sending from the switch a packet that includes a physical memory address that includes the external memory address and information identifying the corresponding external memory; and

wherein each external memory coupled to a memory interface module is assigned a unique identifier, and the information identifying the corresponding external memory comprises the identifier assigned to the corresponding external memory.

2. The integrated circuit of claim 1, wherein the switching circuitry is configured to forward a packet based at least in part on destination information included in a packet to be forwarded.

3. The integrated circuit of claim 2, wherein the tile is configured to determine destination information for the packet based on the identifier.

4. The integrated circuit of claim 3, wherein the destination information identifies a tile coupled to the memory interface module for the corresponding external memory.

5. The integrated circuit of claim 4, wherein the destination information identifies an output port of the switch in the tile coupled to the memory interface module for the corresponding external memory.

6. The integrated circuit of claim 1, wherein each tile further includes a translation lookaside buffer coupled to the processor to translate virtual memory addresses to physical memory addresses.

7. An integrated circuit, comprising:

a plurality of tiles, each tile comprising

a processor, and

a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles; and

a plurality of memory interface modules including circuitry to access a respective external memory, each memory interface module coupled to a switch of at least one tile;

wherein at least some of the tiles are configured to access an address in an external memory by sending from the switch a packet that includes a physical memory address that includes the external memory address and information identifying the corresponding external memory; and

wherein the information identifying the corresponding external memory comprises information identifying a tile coupled to the memory interface module for the corresponding external memory.

8. An integrated circuit,

a plurality of tiles, each tile comprising

a processor,

a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles, and

a translation lookaside buffer coupled to the processor to translate virtual memory addresses to physical memory addresses;

and

a plurality of memory interface modules including circuitry to access a respective external memory, each memory interface module coupled to a switch of at least one tile;

wherein at least some of the tiles are configured to access an address in an external memory by sending from the switch a packet that includes a physical memory address that includes the external memory address and information identifying the corresponding external memory; and

wherein the translation lookaside buffer is configured to insert the information identifying the corresponding external memory into the physical memory address.

9. A method for accessing a plurality of external memories coupled to an integrated circuit, the integrated circuit comprising a plurality of tiles, each tile comprising a processor and a switch, the method comprising:

preparing a packet to access an address in an external memory, the packet including a physical memory address that includes the external memory address and information identifying the corresponding external memory; and

routing the packet through switches of the tiles to the corresponding external memory;

wherein each external memory coupled to the integrated circuit is assigned a unique identifier, and the information identifying the corresponding external memory comprises the identifier assigned to the corresponding external memory.

10. The method of claim 9, wherein routing the packet through switches comprises forwarding a packet based at least in part on destination information included in a packet to be forwarded.

11. The method of claim 10, wherein preparing the packet comprises determining destination information for the packet based on the identifier.

12. The method of claim 11, wherein the destination information identifies a tile coupled to a memory interface module for the corresponding external memory.

13. The method of claim 12, wherein the destination information identifies an output port of the switch in the tile coupled to the memory interface module for the corresponding external memory.

14. The method of claim 9, further comprising translating virtual memory addresses to physical memory addresses.

15. A method for accessing a plurality of external memories coupled to an integrated circuit, the integrated circuit comprising a plurality of tiles, each tile comprising a processor and a switch, the method comprising:

preparing a packet to access an address in an external memory, the packet including a physical memory address that includes the external memory address and information identifying the corresponding external memory; and

routing the packet through switches of the tiles to the corresponding external memory;

wherein the information identifying the corresponding external memory comprises information identifying a tile coupled to a memory interface module for the corresponding external memory.

16. A method for accessing a plurality of external memories coupled to an integrated circuit, the integrated circuit comprising a plurality of tiles, each tile comprising a processor and a switch, the method comprising:

preparing a packet to access an address in an external memory, the packet including a physical memory address that includes the external memory address and information identifying the corresponding external memory;

routing the packet through switches of the tiles to the corresponding external memory; and

translating virtual memory addresses to physical memory addresses;

wherein translating a virtual memory address to a physical memory address comprises inserting the information identifying the corresponding external memory into the physical memory address.