Smart cards having protection circuits therein that inhibit power analysis attacks and methods of operating same

• US 7,620,823 B2
• Filed: 05/02/2003
• Issued: 11/17/2009
• Est. Priority Date: 02/06/2003
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Seo-Kyu
• Primary Examiner(s): Dada; Beemnet W
• Assistant Examiner(s): PAN, JOSEPH T
• Application Number:
  US10/429,084
• Publication Number:
  US 20040158728A1
• Time in Patent Office: 2,391 Days
• Field of Search: 726/26, 726/2, 713/300, 713/1, 713/2, 713/188, 713/194, 380/200, 380/201, 380/255, 380/277, 257/679, 257/312, 257/352, 257/532
• US Class Current: 713/194
• CPC Class Codes: G06K 19/073 Special arrangements for circuits, e.g. for protecting identification code in memory protection against unauthorised use of computer memory G06F12/14
• CPC Class Codes: G06K 19/07363 by preventing analysis of the circuit, e.g. dynamic or static power analysis or current analysis

Abstract

A smart card includes an integrated circuit device having secure information therein. A protection circuit is provided within the smart card. This protection circuit is configured to protect the integrated circuit device, by preventing unauthorized retrieval of the secure information using a power analysis technique. This is done by maintaining at least one power supply line that is electrically coupled to the integrated circuit device at a substantially uniform voltage when the integrated circuit device is active. This uniform voltage operates to mask the operations performed by the integrated circuit device, and thereby conceal these operations from external hardware that may be designed to support the power analysis technique. In particular, a variable capacitor is provided to supply displacement current to the power supply line and the integrated circuit while the capacitance of the capacitor is gradually decreased at an appropriate rate to support a constant supply voltage on the power supply line.

Claims

1. A smart card, comprising:

a substrate;

an integrated circuit device in said substrate; and

a protection circuit in said substrate, said protection circuit configured to inhibit cryptanalytic analysis of said integrated circuit device by maintaining a power supply line that is electrically coupled to said integrated circuit device at a first voltage when said integrated circuit device is active, said protection circuit comprising;

a variable capacitor that is configured to supply displacement current to the power supply line when said integrated circuit is active; and

a control circuit that is configured to increase a value of the variable capacitor in response to detecting an increase in a voltage of the power supply line and is further configured to decrease the value of the variable capacitor in response to detecting a decrease in the voltage of the power supply line.

2. The card of claim 1, wherein said control circuit comprises:

a comparator that is configured to compare the voltage of the power supply line against a reference voltage; and

an up/down counter that is electrically coupled to an output of said comparator.

3. The card of claim 2, wherein said control circuit further comprises:

a digital-to-analog converter having at least one input that is electrically coupled to an output of said up/down counter and an output electrically coupled to the variable capacitor.

4. The card of claim 1, wherein said substrate is a flexible substrate having width and length dimensions that are substantially equivalent to width and length dimensions of a credit card.

5. A smart card, comprising:

a substrate;

an integrated circuit device in said substrate; and

a protection circuit in said substrate, said protection circuit configured to inhibit cryptanalytic analysis of said integrated circuit device by maintaining a power supply line that is electrically coupled to said integrated circuit device at a power supply voltage (V_s), said protection circuit comprising;

a variable capacitor having a capacitance equal to C_v, and a first terminal electrically connected to the power supply line; and

means, electrically coupled to the power supply line and a control terminal of said variable capacitor, for varying the control terminal so that the following relationship is maintained valid over a discharge time interval from time t1 to time t2 when said integrated circuit device is active;

∫

I_d(t)dt=V_s((C_v(t1)−

C_v(t2)),

where I_d(t) equals a magnitude of a displacement current provided from said variable capacitor to the power supply line during the discharge time interval.

6. The card of claim 5, wherein said varying means comprises:

a comparator that is configured to compare a voltage on the power supply line against a reference voltage; and

an up/down counter that is electrically coupled to an output of said comparator.

7. The card of claim 6, wherein said varying means comprises:

a digital-to-analog converter having at least one input that is electrically coupled to an output of said up/down counter and an output electrically coupled to said variable capacitor.

8. The card of claim 5, further comprising an overvoltage protection circuit electrically coupled to the power supply line.

9. A method of operating a smart card having an integrated circuit device and a variable capacitor therein, comprising the step of:

supplying positive displacement current from the variable capacitor to a power supply line connected to the integrated circuit device while simultaneously decreasing a capacitance of the variable capacitor at a sufficient rate to maintain the power supply line at a substantially uniform voltage.

10. The method of claim 9, further comprising the step of:

supplying positive displacement current from the power supply line to the variable capacitor while simultaneously increasing a capacitance of the variable capacitor at a sufficient rate to maintain the power supply line at the substantially uniform voltage.

11. The method of claim 9, wherein decreasing the capacitance of the variable capacitor comprises decrementing the capacitance of the variable capacitor in steps that are synchronized with a clock signal.

12. The method of claim 10, wherein increasing the capacitance of the variable capacitor comprises incrementing the capacitance of the variable capacitor in steps that are synchronized with a clock signal.

13. The method of claim 12, wherein increasing the capacitance of the variable capacitor comprises the steps of:

generating a multi-bit count signal that decreases in-sync with the clock signal; and

converting the multi-bit count signal into an analog signal that is provided to a control terminal of the variable capacitor.